公开(公告)号：US20170098620A1

公开(公告)日：2017-04-06

申请号：US15285250

申请日：2016-10-04

Applicant: Infineon Technologies AG

Inventor： Roman Roth ,  Wolfgang Wagner

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05118 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/4502 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014

Abstract: A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.

公开(公告)号：US20160276558A1

公开(公告)日：2016-09-22

申请号：US14412794

申请日：2014-12-16

Applicant: ILJIN LED CO., LTD.

Inventor： Pil Geun KANG ,  Ho Sub LEE ,  Seong Joo HWANG

IPC: H01L33/62 ,  H01L33/06 ,  H01L33/46

CPC classification number: H01L33/62 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L33/06 ,  H01L33/46 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/0508 ,  H01L2224/05109 ,  H01L2224/05111 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05193 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2933/0066 ,  H01L2924/0105

Abstract: A light-emitting diode having a multilayer bonding pad includes: a P1 layer disposed under a light-emitting structure and configured to improve ohmic contact and adhesion; a P3 layer disposed under the P1 layer and configured to prevent diffusion; a Sn-based metal layer disposed under the P1 layer and configured to enhance soldering weldability and prevent oxidation; a Cu-based P5 layer disposed on the Sn-based metal layer and configured to prevent the diffusion of Sn; and a P4 layer disposed between the P3 layer and the P5 layer and configured to suppress the reaction between the P5 layer and other layers.

Abstract translation: 具有多层接合焊盘的发光二极管包括：设置在发光结构下并被配置为改善欧姆接触和粘附的P1层; P3层，其设置在所述P1层下方并且被配置为防止扩散; 设置在P1层下方的Sn系金属层，其构造为提高焊接性，防止氧化; 设置在所述Sn基金属层上并且被配置为防止Sn的扩散的Cu基P5层; 以及设置在P3层和P5层之间的P4层，并且被配置为抑制P5层与其它层之间的反应。

公开(公告)号：US20080280402A1

公开(公告)日：2008-11-13

申请号：US12110986

申请日：2008-04-28

Applicant: Tomoaki MORIWAKA

Inventor： Tomoaki MORIWAKA

IPC: H01L21/336

CPC classification number: G06K19/07749 ,  G06K19/0775 ,  G06K19/07786 ,  H01L24/29 ,  H01L24/83 ,  H01L29/458 ,  H01L29/66757 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0516 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/83 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Silicide films with high quality are formed with treatment of laser light irradiation, so that miniaturization and higher performance is achieved in a field-effect transistor that is formed over an insulating substrate and has little variation in electric characteristics. An island-shaped semiconductor film including a pair of impurity regions and a channel formation region is formed over an insulating substrate, a first metal film is formed on the pair of impurity regions, and a second metal film that functions as a reflective film is formed over a gate electrode located over the channel formation region with a gate insulating film interposed therebetween. The first metal film is irradiated with laser light and a region where the second metal film is formed reflects the laser light, so that the island-shaped semiconductor film and the first metal film selectively react with each other in the pair of impurity regions.

Abstract translation: 通过激光照射的处理形成高品质的硅化物膜，从而在绝缘基板上形成的场效应晶体管中实现小型化和更高的性能，并且电特性几乎没有变化。 在绝缘基板上形成包括一对杂质区域和沟道形成区域的岛状半导体膜，在一对杂质区域上形成第一金属膜，形成作为反射膜的第二金属膜 在位于通道形成区域上方的栅极电极之间插入栅极绝缘膜。 用激光照射第一金属膜，并且形成第二金属膜的区域反射激光，使得岛状半导体膜和第一金属膜在该对杂质区域中选择性地反应。

公开(公告)号：US20070108562A1

公开(公告)日：2007-05-17

申请号：US11616852

申请日：2006-12-27

Applicant: Young-Hee SONG ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

Inventor： Young-Hee SONG ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

IPC: H01L23/495

CPC classification number: H01L24/06 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05116 ,  H01L2224/05118 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05669 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48471 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099

Abstract: A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region.

Abstract translation: 半导体封装包括具有形成在单元区域和彼此相邻的外围电路区域的集成电路的半导体衬底。 在半导体衬底上形成接合焊盘布线图形。 衬垫重排图案电连接到接合焊盘布线图案。衬垫重排图案包括设置在单元区域的至少一部分上的接合焊盘。

公开(公告)号：US06642627B2

公开(公告)日：2003-11-04

申请号：US10192800

申请日：2002-07-09

Applicant: Young-Hee Song ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

Inventor： Young-Hee Song ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

IPC: H01L2348

CPC classification number: H01L24/05 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05116 ,  H01L2224/05118 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05669 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48471 ,  H01L2224/49113 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10161 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

公开(公告)号：US06576541B2

公开(公告)日：2003-06-10

申请号：US09796268

申请日：2001-02-28

Applicant: Chu-Chin Hu

Inventor： Chu-Chin Hu

IPC: H01L2144

CPC classification number: H05K3/243 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2924/14 ,  H05K3/3473 ,  H05K2203/043 ,  H05K2203/054 ,  Y10T428/26 ,  Y10T428/31678 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2924/013 ,  H01L2924/00014

Abstract: A method for producing bumps on an IC package substrate. The method first deposits a medium layer on a protective layer of the IC package substrate, which has good adherence ability to both the copper layer and the protective layer. Then, a CVD process is applied to deposit a copper layer on the medium layer to form the metal layer. A dry film is thereafter formed on the metal layer and several contact windows are opened therein. A metal pad and a bump are electroplated in the contact windows. Then the dry film is removed, the bumps are protruded out of the substrate with a predetermined height to be solder bumps with an IC chip. Thus, an IC chip no longer needs to form bumps thereon anymore and to save cost and reduce pitch between bumps down to 150 um. Therefore, the improved BGA substrate may be applied on to smaller IC package device to meet the trend for minimizing package sizes.

Abstract translation: 一种用于在IC封装基板上制造凸块的方法。 该方法首先在IC封装基板的保护层上沉积介质层，这对铜层和保护层具有良好的粘附能力。 然后，施加CVD工艺以在介质层上沉积铜层以形成金属层。 此后在金属层上形成干膜，并在其中打开几个接触窗口。 金属垫和凸块在接触窗中电镀。 然后去除干膜，凸起以预定的高度从基板突出出来，成为具有IC芯片的焊料凸块。 因此，IC芯片不再需要在其上形成凸块，并且节省成本并减小凸点之间的间距至150um。 因此，改进的BGA衬底可以应用于较小的IC封装器件以满足最小化封装尺寸的趋势。

公开(公告)号：US08580581B2

公开(公告)日：2013-11-12

申请号：US12943447

申请日：2010-11-10

Applicant: Shigenobu Sekine ,  Yurina Sekine ,  Yoshiharu Kuwana

Inventor： Shigenobu Sekine ,  Yurina Sekine ,  Yoshiharu Kuwana

IPC: H01L21/00

CPC classification number: H01L25/50 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0516 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/10135 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/16146 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01066 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method for manufacturing an electronic device, including a step of aligning and stacking a plurality of substrates, each of the plurality of substrates having a plurality of vertical conductors and magnetic films, the vertical conductors being directed along a thickness direction of the substrate and distributed in a row with respect to a substrate surface, the magnetic films being disposed in place on the substrate surface in a predetermined positional relationship with the vertical conductors, upon aligning the plurality of substrates, the electronic device manufacturing method including a step of applying an external magnetic field to produce a magnetic attractive force between the magnetic films of adjacent stacked substrates and align the vertical conductors by the magnetic attractive force.

Abstract translation: 一种电子装置的制造方法，其特征在于，包括：对准和堆叠多个基板的步骤，所述多个基板中的每一个具有多个垂直导体和磁性膜，所述垂直导体沿着所述基板的厚度方向引导并分布 相对于基板表面成一排地，在对准多个基板时，磁性膜以与垂直导体预定的位置关系被布置在基板表面上的适当位置，该电子设备制造方法包括施加外部 磁场，以在相邻堆叠的衬底的磁性膜之间产生磁吸引力，并通过磁吸引力对准垂直导体。

公开(公告)号：US20120068345A1

公开(公告)日：2012-03-22

申请号：US12883362

申请日：2010-09-16

Applicant: Tobias Schmidt ,  Evelyn Napetschnig ,  Franz Stueckler ,  Anton Pugatschow

Inventor： Tobias Schmidt ,  Evelyn Napetschnig ,  Franz Stueckler ,  Anton Pugatschow

IPC: H01L23/522

CPC classification number: H01L24/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/29082 ,  H01L2224/32227 ,  H01L2224/83805 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process.

Abstract translation: 在各种实施例中，提供层叠。 层叠可以包括载体; 设置在载体上的第一金属; 设置在所述第一金属上的第二金属; 以及设置在第二金属上方的焊料材料或提供与由外部源供应的焊料的接触的材料。 第二金属可以具有至少1800℃的熔融温度，并且在焊接工艺期间和焊接工艺之后至少一个焊料材料中不会或基本上不溶解。

公开(公告)号：US07851352B2

公开(公告)日：2010-12-14

申请号：US12110986

申请日：2008-04-28

Applicant: Tomoaki Moriwaka

Inventor： Tomoaki Moriwaka

IPC: H01L21/4763 ,  H01L21/02

CPC classification number: G06K19/07749 ,  G06K19/0775 ,  G06K19/07786 ,  H01L24/29 ,  H01L24/83 ,  H01L29/458 ,  H01L29/66757 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0516 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/83 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Silicide films with high quality are formed with treatment of laser light irradiation, so that miniaturization and higher performance is achieved in a field-effect transistor that is formed over an insulating substrate and has little variation in electric characteristics. An island-shaped semiconductor film including a pair of impurity regions and a channel formation region is formed over an insulating substrate, a first metal film is formed on the pair of impurity regions, and a second metal film that functions as a reflective film is formed over a gate electrode located over the channel formation region with a gate insulating film interposed therebetween. The first metal film is irradiated with laser light and a region where the second metal film is formed reflects the laser light, so that the island-shaped semiconductor film and the first metal film selectively react with each other in the pair of impurity regions.

Abstract translation: 通过激光照射的处理形成高品质的硅化物膜，从而在绝缘基板上形成的场效应晶体管中实现小型化和更高的性能，并且电特性几乎没有变化。 在绝缘基板上形成包括一对杂质区域和沟道形成区域的岛状半导体膜，在一对杂质区域上形成第一金属膜，形成作为反射膜的第二金属膜 在位于通道形成区域上方的栅极电极之间插入栅极绝缘膜。 用激光照射第一金属膜，并且形成第二金属膜的区域反射激光，使得岛状半导体膜和第一金属膜在该对杂质区域中选择性地反应。

公开(公告)号：US20090174052A1

公开(公告)日：2009-07-09

申请号：US12298285

申请日：2007-05-22

Applicant: Yoshimichi Sogawa ,  Takao Yamazaki ,  Nobuaki Takahashi

Inventor： Yoshimichi Sogawa ,  Takao Yamazaki ,  Nobuaki Takahashi

IPC: H01L23/52

CPC classification number: H01L23/49866 ,  H01L21/563 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05118 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/115 ,  H01L2224/11502 ,  H01L2224/1152 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75702 ,  H01L2224/8121 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3512 ,  H01L2924/3651 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3463 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: In a conventional UBM made of, for example, Cu, Ni, or NiP, there has been a problem that when an electronic component is held in high-temperature conditions for an extended period, the barrier characteristic of the UBM is lost and the bonding strength decreases due to formation of a brittle alloy layer at a bonding interface. The present invention improves the problem of decrease in long-term connection reliability of a solder connection portion after storage at high temperatures. An electronic component comprises the electronic component includes an electrode pad formed on a substrate or a semiconductor element and a barrier metal layer formed to cover the electrode pad and the barrier metal layer comprises a CuNi alloy layer on the side opposite the side in contact with the electrode pad, the CuNi alloy layer containing 15 to 60 at % of Cu and 40 to 85 at % of Ni.

Abstract translation: 在由例如Cu，Ni或NiP制成的常规UBM中，存在如下问题：当电子部件长时间保持在高温条件下时，UBM的阻挡特性丧失， 由于在接合界面处形成脆性合金层，强度降低。 本发明改善了在高温下储存之后焊料连接部分的长期连接可靠性降低的问题。 电子部件包括电子部件，其包括形成在基板或半导体元件上的电极焊盘和形成为覆盖电极焊盘的阻挡金属层，并且阻挡金属层在与所述电极焊盘接触的一侧相反的一侧包括CuNi合金层 电极焊盘，含有15〜60at％的Cu和40〜85at％的Ni的CuNi合金层。