公开(公告)号：US12074106B2

公开(公告)日：2024-08-27

申请号：US18349925

申请日：2023-07-10

Applicant: Applied Materials, Inc.

Inventor： Richard W. Plavidal ,  Albert Lan

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/76841 ,  H01L23/3731 ,  H01L23/3732 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/81 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05684 ,  H01L2224/11009 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2224/13184 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/8113 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13157 ,  H01L2924/00014 ,  H01L2224/13184 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05657 ,  H01L2924/00014

Abstract: Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.

公开(公告)号：US20240274554A1

公开(公告)日：2024-08-15

申请号：US18632532

申请日：2024-04-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TENG-YEN HUANG

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L24/02 ,  H01L2224/02372 ,  H01L2224/03001 ,  H01L2224/03011 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05193 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80379 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0504 ,  H01L2924/0509 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2924/30105

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

公开(公告)号：US20240153902A1

公开(公告)日：2024-05-09

申请号：US18367609

申请日：2023-09-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHENG-FU HUANG ,  SHING-YIH SHIH

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/0215 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05663 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.

公开(公告)号：US11876049B2

公开(公告)日：2024-01-16

申请号：US17100855

申请日：2020-11-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Meng Yan ,  Jia Wen Wang ,  Si Ping Hu ,  Shun Hu

IPC: H01L23/528 ,  H01L23/544 ,  H01L25/065 ,  H10B43/50 ,  H01L23/00 ,  G03F9/00

CPC classification number: H01L23/5283 ,  G03F9/7049 ,  G03F9/7088 ,  G03F9/7092 ,  H01L23/544 ,  H01L24/80 ,  H01L25/0657 ,  H10B43/50 ,  H01L24/05 ,  H01L24/08 ,  H01L2223/54426 ,  H01L2224/04 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/80908 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact and a first bonding alignment mark is formed above the first device layer. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact and a second bonding alignment mark is formed above the second device layer. The first bonding alignment mark is aligned with the second bonding alignment mark, such that the first bonding contact is aligned with the second bonding contact. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact at a bonding interface, and the first bonding alignment mark is in contact with the second bonding alignment mark at the bonding interface.

公开(公告)号：US20230402411A1

公开(公告)日：2023-12-14

申请号：US18238082

申请日：2023-08-25

Applicant: SONY GROUP CORPORATION

Inventor： Masaki HANEDA

IPC: H01L23/00 ,  H01L27/14 ,  H01L25/065 ,  H01L27/146 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L27/14 ,  H01L25/0657 ,  H01L24/80 ,  H01L24/08 ,  H01L24/89 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L2224/08121 ,  H01L2224/05639 ,  H01L2224/05007 ,  H01L2224/05655 ,  H01L2224/08147 ,  H01L2224/80097 ,  H01L2224/80948 ,  H01L2224/05618 ,  H01L2224/05657 ,  H01L2224/80986 ,  H01L2224/0566 ,  H01L24/03 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/80009 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/0104 ,  H01L2924/05442

Abstract: Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.

公开(公告)号：US20230360946A1

公开(公告)日：2023-11-09

申请号：US17738182

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsin YANG ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L21/683 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L24/80 ,  H01L24/05 ,  H01L24/08 ,  H01L24/03 ,  H01L2221/68381 ,  H01L2224/80006 ,  H01L2224/80379 ,  H01L2224/808 ,  H01L2224/03622 ,  H01L2224/0346 ,  H01L2224/03845 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05655 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/05666 ,  H01L2224/08145 ,  H01L28/87

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a contact feature over an insulating layer, forming a first passivation layer over the contact feature, and etching the first passivation layer to form a trench exposing the contact feature. The method also includes forming an oxide layer over the contact feature and the first passivation layer and in the trench, forming a first non-conductive structure over the oxide layer, and patterning the first non-conductive structure to form a gap. The method further includes filling a conductive material in the gap to form a first conductive feature. The first non-conductive structure and the first conductive feature form a first bonding structure. The method further includes attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.

公开(公告)号：US11682640B2

公开(公告)日：2023-06-20

申请号：US17103810

申请日：2020-11-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta Ghate Farooq ,  James J. Kelly

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/03 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/0569 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/05657 ,  H01L2224/05663 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/05684 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078

Abstract: A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

公开(公告)号：US20190237391A1

公开(公告)日：2019-08-01

申请号：US16329170

申请日：2016-10-27

Applicant: Intel Corporation

Inventor： Seshu V. SATTIRAJU ,  Krishna Prakash GANESAN ,  Ashish BHATIA ,  Vinay SRIRAM ,  John MUIRHEAD ,  Hiten KOTHARI ,  Aloysius A. GUNAWAN ,  Lavanya ARYASOMAYAJULA ,  Shravan GOWRISHANKAR ,  Sriram PATTABHIRAMAN ,  Sudipto GUHA

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/822

CPC classification number: H01L23/481 ,  H01L21/48 ,  H01L21/76876 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/00 ,  H01L23/48 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05657 ,  H01L2224/06153 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/335 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/014

Abstract: A stacked-chip assembly including a plurality of IC chips or die that are stacked, and electrically coupled by solder bonds. In accordance with some embodiments described further below, the solder bonds are to contact a back-side land that includes a diffusion barrier to reduce intermetallic formation and/or other solder-induced reliability issues. The back-side land may include an electrolytic nickel (Ni) barrier layer separating solder from a back-side redistribution layer trace. This electrolytic Ni may be of high purity, which at least in part, may enable the backside metallization stack to be of minimal thickness while still functioning as a diffusion barrier. In some embodiments, the back-side land composition and architecture is distinct from a front-side land composition and/or architecture.

公开(公告)号：US20180204873A1

公开(公告)日：2018-07-19

申请号：US15921441

申请日：2018-03-14

Applicant: Sony Corporation

Inventor： Atsushi Okuyama

IPC: H01L27/146 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L24/06 ,  H01L24/09 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14634 ,  H01L2224/05547 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/0558 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0903 ,  H01L2224/095 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/00014

Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

公开(公告)号：US20170338169A1

公开(公告)日：2017-11-23

申请号：US15600857

申请日：2017-05-22

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L24/48 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02288 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/0346 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45611 ,  H01L2224/45618 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45649 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/45664 ,  H01L2224/45666 ,  H01L2224/4567 ,  H01L2224/45671 ,  H01L2224/45672 ,  H01L2224/4568 ,  H01L2224/45686 ,  H01L2224/4569 ,  H01L2224/45693 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48507 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/85801 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01046 ,  H01L2224/45669 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01056 ,  H01L2924/00 ,  H01L2224/43848

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.