公开(公告)号：US12191233B2

公开(公告)日：2025-01-07

申请号：US17876376

申请日：2022-07-28

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Belgacem Haba ,  Thomas Workman ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Rajesh Katkar

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/32 ,  H01L23/467 ,  H01L23/473 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.

公开(公告)号：US20250006689A1

公开(公告)日：2025-01-02

申请号：US18513145

申请日：2023-11-17

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Gaius Gillman Fountain, JR. ,  Thomas Workman ,  Guilian Gao ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L25/065

Abstract: Disclosed is a bonded structure including a substrate that includes a surface and at least one bumper extending above the surface by a bumper height. The bonded structure further includes at least one die directly bonded to the surface adjacent the bumper.

公开(公告)号：US20250006679A1

公开(公告)日：2025-01-02

申请号：US18391173

申请日：2023-12-20

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Jeremy Alfred Theil ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Belgacem Haba ,  Laura Wills Mirkarimi

IPC: H01L23/00

Abstract: A structure includes a first substrate including a first layer having at least one electrically conductive first portion and at least one electrically insulative second portion and a second substrate including a second layer having at least one electrically conductive third portion and at least one electrically insulative fourth portion. The structure further includes an interface layer having at least one electrically conductive oxide material between the first layer and the second layer. The at least one electrically conductive oxide material includes at least one first region between and in electrical communication with the at least one electrically conductive first portion and the at least one electrically conductive third portion, and at least one second region between the at least one electrically insulative second portion and the at least one electrically insulative fourth portion.

公开(公告)号：US20240371850A1

公开(公告)日：2024-11-07

申请号：US18541869

申请日：2023-12-15

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Guilian Gao ,  Gaius Gillman Fountain, JR.

IPC: H01L25/00 ,  H01L21/18 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065

Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

公开(公告)号：US20240332227A1

公开(公告)日：2024-10-03

申请号：US18194544

申请日：2023-03-31

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC

Inventor： Cyprian Emeka Uzoh ,  Oliver Zhao

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/03614 ,  H01L2224/0382 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/03845 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0543

Abstract: A semiconductor element having an interconnect bonding layer with a contact pad and a plasma damage-free low-k dielectric material is disclosed. The contact pad connects an underlying conductive feature through an intervening via. A thin dielectric layer is disposed on and covering the entire sidewalls of the contact pad, the intervening via and the underlying conductive feature, and making an approximately right angle turn to extend along an interface between the low-k dielectric material and a first dielectric layer that at least partially bury the underlying contact feature.

公开(公告)号：US20240312953A1

公开(公告)日：2024-09-19

申请号：US18671851

申请日：2024-05-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Laura Wills Mirkarimi ,  Gaius Gillman Fountain, JR. ,  Cyprian Emeka Uzoh

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80143 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

公开(公告)号：US20240186268A1

公开(公告)日：2024-06-06

申请号：US18523702

申请日：2023-11-29

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/053 ,  H01L23/3157 ,  H01L24/08 ,  H01L2224/08225

Abstract: A bonded structure is disclosed. The bonded structure can include a carrier including a surface having a first region and a second region, an integrated device die directly bonded to the first region of the carrier, and a frame structure that is disposed on the second region. The frame structure can be a continuous frame structure. The frame structure can have a first elongate frame element and a second elongate frame element that are positioned between the integrated device die and the second section. At least a portion of the second region between the first frame element and the second frame element can be free from the frame structure.

公开(公告)号：US11955445B2

公开(公告)日：2024-04-09

申请号：US17836840

申请日：2022-06-09

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Bongsub Lee ,  Gaius Gillman Fountain, Jr. ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/94 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/08146 ,  H01L2224/80896

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

公开(公告)号：US20240105674A1

公开(公告)日：2024-03-28

申请号：US18461372

申请日：2023-09-05

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Thomas Workman

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/80365 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/059

Abstract: Bonded structures and methods of forming a bonded structure are disclosed. A bonded structure can include a first element and a second element. The first element includes a first non-conductive field region and a first conductive feature. The second element includes a second non-conductive field region and a second conductive feature. The second element is directly bonded to the first element along a bonding interface such that the first non-conductive field region is directly bonded to the second non-conductive field region without an intervening adhesive, and the first conductive feature is directly bonded to the second conductive feature without an intervening adhesive. A first portion of the first non-conductive field region at the bonding interface has a first surface roughness and a second portion of the first non-conductive field region at the bonding interface has a second surface roughness. The second surface roughness can be different from the first surface roughness. The first surface roughness can be greater than 6 Å rms.

公开(公告)号：US11894326B2

公开(公告)日：2024-02-06

申请号：US17370576

申请日：2021-07-08

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/0347 ,  H01L2224/0362 ,  H01L2224/0384 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/03845 ,  H01L2224/05013 ,  H01L2224/05015 ,  H01L2224/05026 ,  H01L2224/05076 ,  H01L2224/05082 ,  H01L2224/05105 ,  H01L2224/05109 ,  H01L2224/05111 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05551 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80375 ,  H01L2224/80895 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05609 ,  H01L2924/00014 ,  H01L2224/05605 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014

Abstract: A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.