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1.发明公开公开(公告)号：US20240055407A1
公开(公告)日：2024-02-15
申请号：US18366569
申请日：2023-08-07
Inventor： Thomas Workman , Belgacem Haba
IPC: H01L25/065 , H01L23/00 , G01R31/28 , H01L23/528
CPC classification number: H01L25/0657 , H01L24/08 , G01R31/2884 , H01L23/528 , H01L2224/08148 , H01L2924/1431
Abstract: A bonded structure for debugging integrated circuit devices and a method for debugging integrated circuit devices is disclosed. The bonded structure may comprise a debugging element and an integrated circuit device. The debugging element may comprise a debugging circuitry. The debugging element may be bonded to an integrated circuit device. The debugging element may be configured to debug the integrated circuit device.
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公开(公告)号：US20240387439A1
公开(公告)日：2024-11-21
申请号：US18784724
申请日：2024-07-25
Inventor： Belgacem Haba , Laura Wills Mirkarimi , Javier A. DeLaCruz , Rajesh Katkar , Cyprian Emeka Uzoh , Guilian Gao , Thomas Workman
Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.
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3.发明公开公开(公告)号：US20240203948A1
公开(公告)日：2024-06-20
申请号：US18589231
申请日：2024-02-27
Inventor： Cyprian Emeka Uzoh , Rajesh Katkar , Thomas Workman , Guilian Gao , Gaius Gillman Fountain, JR. , Laura Wills Mirkarimi , Belgacem Haba , Gabriel Z. Guevara , Joy Watanabe
IPC: H01L25/065 , H01L21/56 , H01L23/00 , H01L23/31
CPC classification number: H01L25/0657 , H01L21/561 , H01L23/3121 , H01L24/97 , H01L2224/0401 , H01L2924/3511 , H01L2924/35121
Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
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公开(公告)号：US20240096683A1
公开(公告)日：2024-03-21
申请号：US18368971
申请日：2023-09-15
Inventor： Cyprian Emeka Uzoh , Aaron Todd Francis , Gabriel Guevara , Thomas Workman , Dominik Suwito
IPC: H01L21/683
CPC classification number: H01L21/6835 , H01L2221/68309 , H01L2221/68313 , H01L2221/68354
Abstract: Embodiments herein are generally directed to die cleaning frames for processing and handling singulated devices and methods related thereto. The die cleaning frames may be used advantageously to minimize contact with device surfaces during post-singulation processing and to facilitate a pick and place bonding process without touching the active side of the cleaned device. Thus, the die cleaning frames and methods described herein eliminate the need for undesirable contact with clean and prepared active sides of the devices during a direct placement die-to-wafer bonding process. In one embodiment, a carrier configured to support a singulated device in a die pocket region may include a carrier plate and a frame that surrounds the carrier plate and is integrally formed therewith. The carrier plate may include a first surface and an opposite second surface, and one or more sidewalls that define an opening disposed through and extending between the first and second surfaces. Each of the sidewalls may include one or more protuberances that collectively determine a rectangular boundary of the die pocket region. Some of the protuberances may include a die supporting surface that extends beneath the die pocket region.
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公开(公告)号：US20250054837A1
公开(公告)日：2025-02-13
申请号：US18924480
申请日：2024-10-23
Inventor： Thomas Workman , Ron Zhang , Kyong-Mo Bang , Belgacem Haba , Gaius Gillman Fountain, JR.
IPC: H01L23/473 , H01L23/00 , H01L23/367
Abstract: A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20250006520A1
公开(公告)日：2025-01-02
申请号：US18239394
申请日：2023-08-29
Inventor： Cyprian Emeka Uzoh , Thomas Workman , Gabriel Z. Guevara
IPC: H01L21/67 , H01L21/683
Abstract: Embodiments herein are generally directed to ejection assemblies for singulated dies and thinned wafers and methods related thereto. Die ejection assemblies may be used to minimize cracking or deformation of dies during post-singulation processing. Thus, the die ejection assemblies and methods described herein reduce the number of dies rejected after singulation and the number of failures during a die bonding process. In one general aspect, an apparatus for removing singulated dies from a dicing tape is provided. The apparatus may include a die ejector assembly, which may include a vacuum plate configured to engage with a portion of the dicing tape. A die ejector may be disposed in an ejector opening of the vacuum plate. One or more actuators may be configured to move at least a portion of the die ejector in a lateral direction relative to the upper surface of the vacuum plate.
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公开(公告)号：US20240079376A1
公开(公告)日：2024-03-07
申请号：US18461290
申请日：2023-09-05
Inventor： Dominik Suwito , Thomas Workman , Rajesh Katkar , Laura Wills Mirkarimi
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/08 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948
Abstract: Bonded structures and methods of direct hybrid bonding are disclosed. Non-conductive regions of two elements, such as dies or wafers, are first bonded together to form a bonded structure. Aligned conductive regions of the bonded structure, such as metal pads or traces, are then annealed to expand and bridge a gap between them. The anneal includes rapid thermal processing (RTP), such as with radiant heating. The bond interface between the first and second conductive features includes rapid growth structure(s) indicative of the inclusion of RTP in the anneal. Additional non-RTP anneal phases can also be employed.
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公开(公告)号：US20230299029A1
公开(公告)日：2023-09-21
申请号：US18183828
申请日：2023-03-14
Inventor： Jeremy Alfred Theil , Thomas Workman , Cyprian Emeka Uzoh , Jesus Perez , Pawel Mrozek
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L2224/0801 , H01L2224/08111 , H01L2224/08503
Abstract: An element and a bonded structure including the element are disclosed. The element can include a non-conductive region having a cavity extending at least partially through a thickness of the non-conductive region from the contact surface, and a contact feature formed in the cavity. The non-conductive region is configured to directly bond to a non-conductive region of a second element. The contact pad of the element is configured to directly bond to a contact pad of the second element. The contact pad can include a first conductive material and a second conductive material. The first conductive material can have a unit cell size greater than a unit cell size of the second conductive material. The first conductive material can be a metal alloying material. The first conductive material can be a metal silicide and the second conductive material can be a metal. A bonded conductive contact can include a conductive material and an alloying element, and an amount of the alloying element can vary through a thickness of the bonded conductive contact.
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公开(公告)号：US20230268300A1
公开(公告)日：2023-08-24
申请号：US18173690
申请日：2023-02-23
Inventor： Cyprian Emeka Uzoh , Rajesh Katkar , Thomas Workman , Gaius Gillman Fountain, Jr. , Guilian Gao , Jeremy Alfred Theil , Gabriel Z. Guevara , Kyong-Mo Bang , Laura Wills Mirkarimi
IPC: H01L23/00 , H01L25/16 , H01L25/065 , H01L23/498 , H01L23/48
CPC classification number: H01L24/08 , H01L25/16 , H01L25/0657 , H01L25/0655 , H01L25/0652 , H01L23/49838 , H01L23/481 , H01L24/80 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2225/06527 , H01L2924/1011 , H01L2924/1815 , H01L2924/182 , H01L2224/08145 , H01L2224/08121 , H01L2224/08225
Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.
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公开(公告)号：US12080672B2
公开(公告)日：2024-09-03
申请号：US16874527
申请日：2020-05-14
Inventor： Belgacem Haba , Laura Wills Mirkarimi , Javier A. DeLaCruz , Rajesh Katkar , Cyprian Emeka Uzoh , Guilian Gao , Thomas Workman
CPC classification number: H01L24/32 , H01L23/3107 , H01L24/27 , H01L24/29 , H01L24/83 , H01L2224/29187 , H01L2224/32145 , H01L2224/32225 , H01L2224/83005 , H01L2224/83896
Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.
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