公开(公告)号：US20240243085A1

公开(公告)日：2024-07-18

申请号：US18517681

申请日：2023-11-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist

IPC: H01L23/00 ,  H01L21/50 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/036 ,  H01L2224/03616 ,  H01L2224/03825 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/0556 ,  H01L2224/05561 ,  H01L2224/05562 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08112 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/80031 ,  H01L2224/80035 ,  H01L2224/80047 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/8019 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2225/06513

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：US11830838B2

公开(公告)日：2023-11-28

申请号：US17677161

申请日：2022-02-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist

IPC: H01L23/00 ,  H01L21/50 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/03825 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08112 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/8019 ,  H01L2224/80031 ,  H01L2224/80035 ,  H01L2224/80047 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2225/06513 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/29339 ,  H01L2924/00014 ,  H01L2224/29386 ,  H01L2224/80895 ,  H01L2924/053 ,  H01L2224/80986 ,  H01L2224/80896 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05686 ,  H01L2924/04941 ,  H01L2224/05686 ,  H01L2924/04953 ,  H01L2224/05684 ,  H01L2924/049 ,  H01L2224/05676 ,  H01L2924/053 ,  H01L2224/05681 ,  H01L2924/01014 ,  H01L2924/049 ,  H01L2224/05666 ,  H01L2924/01014 ,  H01L2924/049 ,  H01L2224/05684 ,  H01L2924/01005 ,  H01L2924/049 ,  H01L2224/05655 ,  H01L2924/051 ,  H01L2924/00014 ,  H01L2224/05657 ,  H01L2924/01074 ,  H01L2224/05657 ,  H01L2924/01074 ,  H01L2924/042

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：US20180226390A1

公开(公告)日：2018-08-09

申请号：US15869808

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil Kyu KANG ,  Seok Ho KIM ,  Tae Yeong KIM ,  Kwang Jin MOON ,  Ho Jin LEE

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/187 ,  H01L21/76898 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73204 ,  H01L2224/80047 ,  H01L2224/80048 ,  H01L2224/8012 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/3512 ,  H01L2224/80001 ,  H01L2224/81 ,  H01L2924/00014

Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.

公开(公告)号：US20140151823A1

公开(公告)日：2014-06-05

申请号：US13953238

申请日：2013-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C.S. Chou

IPC: B81B3/00

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。

公开(公告)号：US20120091587A1

公开(公告)日：2012-04-19

申请号：US13251269

申请日：2011-10-02

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/522

CPC classification number: H01L21/76232 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/16 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/80006 ,  H01L2224/80009 ,  H01L2224/80047 ,  H01L2224/802 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01066 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

Abstract: A 3D IC based system comprising a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper; a second mono-crystallized semiconductor layer comprising second transistors and overlaying the metal layer; wherein the second mono-crystallized semiconductor layer thickness is less than 150 nm, and wherein at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.

Abstract translation: 一种基于3D IC的系统，包括包括第一晶体管的第一半导体层，其中所述第一晶体管通过包括铝或铜的至少一个金属层互连; 第二单结晶半导体层，包括第二晶体管并覆盖所述金属层; 其中所述第二单结晶半导体层厚度小于150nm，并且其中所述第二晶体管中的至少一个为N型晶体管，并且所述第二晶体管中的至少一个为P型晶体管。

公开(公告)号：US20190237419A1

公开(公告)日：2019-08-01

申请号：US16383455

申请日：2019-04-12

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Paul M. ENQUIST

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/50 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/036 ,  H01L2224/03616 ,  H01L2224/03825 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05561 ,  H01L2224/05562 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08112 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/80031 ,  H01L2224/80035 ,  H01L2224/80047 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/8019 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2224/29339 ,  H01L2224/29386 ,  H01L2924/053 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/049 ,  H01L2924/01014 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/051 ,  H01L2924/042

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：US09859246B2

公开(公告)日：2018-01-02

申请号：US14917318

申请日：2014-12-18

Applicant: EV GROUP E. THALLNER GMBH

Inventor： Andreas Fehkuhrer

IPC: H01L21/00 ,  H01L23/00 ,  B32B37/00 ,  H01L21/18 ,  H01L21/304 ,  H01L21/67 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L23/544 ,  B32B38/18

CPC classification number: H01L24/80 ,  B32B37/0046 ,  B32B38/1841 ,  B32B38/1858 ,  B32B2309/105 ,  B32B2457/14 ,  H01L21/187 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6831 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/08 ,  H01L24/74 ,  H01L24/75 ,  H01L24/94 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/0224 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/0384 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/75251 ,  H01L2224/75272 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/75724 ,  H01L2224/75725 ,  H01L2224/75734 ,  H01L2224/75735 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/80 ,  H01L2224/80003 ,  H01L2224/80006 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/8002 ,  H01L2224/80047 ,  H01L2224/80051 ,  H01L2224/80093 ,  H01L2224/80099 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80209 ,  H01L2224/80213 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2221/68304

Abstract: A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

公开(公告)号：US20170221856A1

公开(公告)日：2017-08-03

申请号：US15519542

申请日：2015-10-19

Applicant: BONDTECH CO., LTD.

Inventor： Akira YAMAUCHI

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/67

CPC classification number: H01L24/83 ,  B23K20/023 ,  B23K20/233 ,  B23K20/24 ,  B23K37/0408 ,  B23K37/047 ,  B23K2101/40 ,  B23K2103/50 ,  H01L21/187 ,  H01L21/67092 ,  H01L21/67259 ,  H01L21/68 ,  H01L21/6831 ,  H01L21/6838 ,  H01L21/68735 ,  H01L23/544 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/7501 ,  H01L2224/75102 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75272 ,  H01L2224/75303 ,  H01L2224/75305 ,  H01L2224/757 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/75724 ,  H01L2224/75725 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/759 ,  H01L2224/75901 ,  H01L2224/7592 ,  H01L2224/75981 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/8003 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80203 ,  H01L2224/80213 ,  H01L2224/80893 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80908 ,  H01L2224/80986 ,  H01L2224/83009 ,  H01L2224/8309 ,  H01L2224/83896 ,  H01L2224/83908 ,  H01L2224/94 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2224/8001 ,  H01L2224/80009 ,  H01L2224/80121

Abstract: A production of voids between substrates is prevented when the substrates are bonded together, and the substrates are bonded together at a high positional precision while suppressing a strain. A method for bonding a first substrate and a second substrate includes a step of performing hydrophilization treatment to cause water or an OH containing substance to adhere to bonding surface of the first substrate and the bonding surface of the second substrate, a step of disposing the first substrate and the second substrate with the respective bonding surfaces facing each other, and bowing the first substrate in such a way that a central portion of the bonding surface protrudes toward the second substrate side relative to an outer circumferential portion of the bonding surface, a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate at the respective central portions, and a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate across the entirety of the bonding surfaces, decreasing a distance between the outer circumferential portion of the first substrate and an outer circumferential portion of the second substrate with the respective central portions abutting each other at a pressure that maintains a non-bonded condition.

公开(公告)号：US09318666B2

公开(公告)日：2016-04-19

申请号：US14085804

申请日：2013-11-21

Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.

Inventor： Hsing-Fen Lo ,  Lung-Hsin Chen

IPC: H01L21/00 ,  H01L27/15 ,  H01L29/267 ,  H01L31/12 ,  H01L33/00 ,  H01L33/48 ,  H01L23/00 ,  H01L33/54 ,  H01L33/62

CPC classification number: H01L33/486 ,  H01L24/97 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/16245 ,  H01L2224/80047 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2933/005 ,  H01L2933/0066 ,  H01L2924/00

Abstract: An LED device includes a substrate having a top surface and a bottom surface. The substrate defines a through hole at a center thereof. The LED device also includes an electrode board. The electrode board defines a concave portion at a center thereof, and a convex portion connected to and surrounding two sides of the concave portion. The concave portion includes a first electrode and a second electrode isolated from each other, and is located in the through hole of the substrate. A bottommost surface of the concave portion is substantially coplanar with the bottom surface of the substrate, and a top surface of the convex portion is substantially coplanar with the top surface of the substrate. An LED chip is arranged on the concave portion, and is electrically connected to the first electrode and the second electrode. A method for manufacturing plural such LED devices is also provided.

Abstract translation: LED装置包括具有顶表面和底表面的基底。 基板在其中心处形成通孔。 LED装置还包括电极板。 电极板在其中央形成有凹部，与凹部的两侧连接并包围的凸部。 凹部包括彼此隔离的第一电极和第二电极，并且位于基板的通孔中。 凹部的最下表面与基板的底面基本共面，并且凸部的顶面与基板的顶面基本共面。 LED芯片设置在凹部上，与第一电极和第二电极电连接。 还提供了一种用于制造多个这样的LED器件的方法。

公开(公告)号：US08742595B1

公开(公告)日：2014-06-03

申请号：US13953238

申请日：2013-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C. S. Chou

IPC: H01L21/58 ,  H01L23/48

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。