公开(公告)号：US20140151823A1

公开(公告)日：2014-06-05

申请号：US13953238

申请日：2013-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C.S. Chou

IPC: B81B3/00

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。

公开(公告)号：US20140131874A1

公开(公告)日：2014-05-15

申请号：US14162140

申请日：2014-01-23

Applicant: Sony Corporation

Inventor： Yoshihisa Kagawa ,  Naoki Komai

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76838 ,  H01L23/53209 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03505 ,  H01L2224/03616 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2224/80004 ,  H01L2224/80011 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: A semiconductor apparatus, electronic device, and method of manufacturing the semiconductor apparatus are disclosed. In one example, the semiconductor apparatus comprises a first semiconductor part that includes a first wiring, and a second semiconductor part that is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring. A metallic oxide is formed in at least one of the first wiring and the second wiring.

Abstract translation: 公开了一种半导体装置，电子装置和半导体装置的制造方法。 在一个示例中，半导体装置包括第一半导体部分，其包括第一布线，第二半导体部分粘附到第一半导体部分，并且包括电连接到第一布线的第二布线。 金属氧化物形成在第一布线和第二布线中的至少一个中。

公开(公告)号：US11694989B2

公开(公告)日：2023-07-04

申请号：US17492711

申请日：2021-10-04

Applicant: SAULTECH TECHNOLOGY CO., LTD.

Inventor： Yen Hao Lu

IPC: H01L21/00 ,  H01L23/00

CPC classification number: H01L24/80 ,  H01L24/74 ,  H01L2224/8009 ,  H01L2224/80895

Abstract: A die bonding method with corner or side contact without impact force includes the steps: picking up a die by a die bonding device, wherein a surface of the die has no solder and bump; moving the die to one side of a die placement area of a substrate, wherein the substrate has no solder and bump; blowing one corner or one side of the die a positive pressure from the die bonding device to bend the corner/side to contact the die placement area; forming a bonding wave after the corner/side of the die contacting the die placement area, and spreading the bonding wave from the corner/side to opposite corner/side of the die, and separating the die from the die bonding device gradually and bonding the die on the die placement area; and bonding the die on the die placement area completely.

公开(公告)号：US20180151436A1

公开(公告)日：2018-05-31

申请号：US15573699

申请日：2016-05-12

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Aurélie TAUZIN ,  Bruno IMBERT

IPC: H01L21/78 ,  H01L21/324 ,  H01L23/00

CPC classification number: H01L21/7806 ,  H01L21/30612 ,  H01L21/3245 ,  H01L21/76254 ,  H01L24/80 ,  H01L31/0725 ,  H01L31/0735 ,  H01L2224/80004 ,  H01L2224/80011 ,  H01L2224/80055 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80894 ,  H01L2224/80948 ,  H01L2924/10329 ,  H01L2924/10335

Abstract: The method is carried out of a first substrate having a first layer made of a first material with a second substrate having a second layer made of a second material, the first material and the second material being of different natures and selected from alloys of elements of columns III and V, the method having the steps of: a) providing the first substrate and the second substrate, b) bringing the first substrate into contact with the second substrate so as to form a bonding interface between the first layer and the second layer, c) performing a first heat treatment at a first predefined temperature, d) thinning one of the substrates, e) depositing, at a temperature less than or equal to the first predefined temperature, a barrier layer, on the thinned substrate, and f) performing a second heat treatment at a second predefined temperature, greater than the first predefined temperature.

公开(公告)号：US20240014153A1

公开(公告)日：2024-01-11

申请号：US18257674

申请日：2021-12-13

Applicant: Tokyo Electron Limited

Inventor： Takashi FUJIBAYASHI ,  Kenji OUCHI

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/08 ,  H01L24/05 ,  H01L24/83 ,  H01L2224/03616 ,  H01L2224/03452 ,  H01L2224/08501 ,  H01L2224/08237 ,  H01L2224/08147 ,  H01L2224/8009 ,  H01L2224/80143 ,  H01L2224/80048

Abstract: A substrate bonding system in one manner of the present disclosure includes a surface treatment module configured to perform plasma processing on a surface of a substrate. The substrate bonding system includes a deposition module coupled to the surface treatment module such that the substrate is transferred to the deposition module without being exposed to atmosphere, the deposition module being configured to perform a deposition process on the substrate on which the plasma processing is performed in the surface treatment module. The substrate bonding system includes a bonding module coupled to the deposition module such that the substrate is transferred to the bonding module without exposing the substrate to the atmosphere, the bonding module being configured to bond substrates on which the deposition process is performed in the deposition module, to form a bonded body.

公开(公告)号：US09437568B2

公开(公告)日：2016-09-06

申请号：US14518389

申请日：2014-10-20

Applicant: Kabushiki Kaisha Toshiba

Inventor： Atsuko Kawasaki

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/76 ,  H01L21/302 ,  H01L21/461 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/24 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/215 ,  H01L2224/24146 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/80001

Abstract: Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

Abstract translation: 某些实施例提供一种用于制造半导体器件的方法，包括形成第一互连层，该第一互连层具有从第一互连层的表面露出的第一导电层和第一绝缘层，形成具有第二导电层的第二互连层和 第二绝缘层，其从第二互连层的表面露出，通过使第一绝缘层的表面的部分区域低于第一绝缘层的表面，在第一绝缘层的表面上形成第一非接合表面 导电层，所述部分区域包含所述第一导电层的周围环境，并且连接所述第一导电层的表面和所述第二导电层的表面，并且将除了所述第一非接合表面和所述表面之外的所述第一绝缘层的表面 的第二绝缘层。

公开(公告)号：US20150162294A1

公开(公告)日：2015-06-11

申请号：US14518389

申请日：2014-10-20

Applicant: Kabushiki Kaisha Toshiba

Inventor： Atsuko KAWASAKI

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/24 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/215 ,  H01L2224/24146 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/80001

Abstract: Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

Abstract translation: 某些实施例提供一种用于制造半导体器件的方法，包括形成第一互连层，该第一互连层具有从第一互连层的表面露出的第一导电层和第一绝缘层，形成具有第二导电层的第二互连层和 第二绝缘层，其从第二互连层的表面露出，通过使第一绝缘层的表面的部分区域低于第一绝缘层的表面，在第一绝缘层的表面上形成第一非接合表面 导电层，所述部分区域包含所述第一导电层的周围环境，并且连接所述第一导电层的表面和所述第二导电层的表面，并且将除了所述第一非接合表面和所述表面之外的所述第一绝缘层的表面 的第二绝缘层。

公开(公告)号：US20230299040A1

公开(公告)日：2023-09-21

申请号：US17699024

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Jay Prakash Gupta ,  Souvik Ghosh ,  Kimin Jun ,  Bhupendra Kumar ,  Shashi Vyas ,  Anup Pancholi

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/08 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03849 ,  H01L2224/08147 ,  H01L2224/05687 ,  H01L2224/05147 ,  H01L2224/05666 ,  H01L2224/05187 ,  H01L2224/8009 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80948 ,  H01L2924/35121

Abstract: A microelectronic assembly and a method of forming same. The assembly includes: first and second microelectronic structures; and an interface layer between the two microelectronic structures including dielectric portions in registration with dielectric layers of each of the microelectronic structures, and electrically conductive portions in registration with electrically conductive structures of each of the microelectronic structures, wherein the dielectric portions include an oxide of a metal, and the electrically conductive portions include the metal.

公开(公告)号：US09379006B2

公开(公告)日：2016-06-28

申请号：US14162140

申请日：2014-01-23

Applicant: Sony Corporation

Inventor： Yoshihisa Kagawa ,  Naoki Komai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L21/76838 ,  H01L23/53209 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03505 ,  H01L2224/03616 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2224/80004 ,  H01L2224/80011 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: A semiconductor apparatus, electronic device, and method of manufacturing the semiconductor apparatus are disclosed. In one example, the semiconductor apparatus comprises a first semiconductor part that includes a first wiring, and a second semiconductor part that is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring. A metallic oxide is formed in at least one of the first wiring and the second wiring.

Abstract translation: 公开了一种半导体装置，电子装置和半导体装置的制造方法。 在一个示例中，半导体装置包括第一半导体部分，其包括第一布线，第二半导体部分粘附到第一半导体部分，并且包括电连接到第一布线的第二布线。 金属氧化物形成在第一布线和第二布线中的至少一个中。

公开(公告)号：US08497148B2

公开(公告)日：2013-07-30

申请号：US13189057

申请日：2011-07-22

Applicant: Bruce C. S. Chou

Inventor： Bruce C. S. Chou

IPC: H01L21/58 ,  H01L23/48

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。