公开(公告)号：US08742595B1

公开(公告)日：2014-06-03

申请号：US13953238

申请日：2013-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C. S. Chou

IPC: H01L21/58 ,  H01L23/48

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。

公开(公告)号：US08664763B2

公开(公告)日：2014-03-04

申请号：US13416412

申请日：2012-03-09

Applicant: Yoshihisa Kagawa ,  Naoki Komai

Inventor： Yoshihisa Kagawa ,  Naoki Komai

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76838 ,  H01L23/53209 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03505 ,  H01L2224/03616 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2224/80004 ,  H01L2224/80011 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: Disclosed herein is a semiconductor apparatus including: a first semiconductor part including a first wiring; a second semiconductor part which is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring; and a metallic oxide formed by a reaction between oxygen and a metallic material which reacts with oxygen more easily than hydrogen does, the metallic oxide having been diffused into a region which includes a joint interface between the first wiring and the second wiring and the inside of at least one of the first wiring and the second wiring.

Abstract translation: 本发明公开了一种半导体装置，包括：第一半导体部件，包括第一布线; 第二半导体部分，其粘附到第一半导体部分，并且包括电连接到第一布线的第二布线; 以及通过氧与金之间的反应比金更容易地与氧反应形成的金属氧化物，所述金属氧化物已经扩散到包括第一布线和第二布线之间的接合界面的区域中，以及内部 第一布线和第二布线中的至少一个。

公开(公告)号：US20130020718A1

公开(公告)日：2013-01-24

申请号：US13189057

申请日：2011-07-22

Applicant: Bruce C.S. Chou

Inventor： Bruce C.S. Chou

IPC: H01L21/58 ,  H01L23/48

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。

公开(公告)号：US20240021549A1

公开(公告)日：2024-01-18

申请号：US17866209

申请日：2022-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  National Yang Ming Chiao Tung University

Inventor： Chih CHEN ,  Hsiang-Hou TSENG

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L25/0657 ,  H01L25/0652 ,  H01L25/0655 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05639 ,  H01L2224/80203 ,  H01L2224/80092 ,  H01L2224/05147 ,  H01L2224/05083 ,  H01L2224/05573 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05026 ,  H01L2224/94 ,  H01L24/94 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/80439 ,  H01L2224/97 ,  H01L21/561

Abstract: A method includes forming a first connector and a second connector over a first wafer and a second wafer, respectively, in which each of the first and second connectors are formed by forming an opening in a dielectric layer; depositing a first metal layer in the opening, in which the first metal layer has a nano-twinned structure with (111) orientation; and depositing a second metal layer over the first metal layer, the second metal layer and the first metal layer being made of different materials, in which the second metal layer has a nano-twinned structure with (111) orientation; attaching the first wafer to the second wafer, such that that the second metal layer of the first connector on the first wafer is in contact with the second metal layer of the second connector on the second wafer; and performing a thermo-compression process to bond the first and second wafers.

公开(公告)号：US20140151823A1

公开(公告)日：2014-06-05

申请号：US13953238

申请日：2013-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C.S. Chou

IPC: B81B3/00

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。

公开(公告)号：US20140131874A1

公开(公告)日：2014-05-15

申请号：US14162140

申请日：2014-01-23

Applicant: Sony Corporation

Inventor： Yoshihisa Kagawa ,  Naoki Komai

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76838 ,  H01L23/53209 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03505 ,  H01L2224/03616 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2224/80004 ,  H01L2224/80011 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: A semiconductor apparatus, electronic device, and method of manufacturing the semiconductor apparatus are disclosed. In one example, the semiconductor apparatus comprises a first semiconductor part that includes a first wiring, and a second semiconductor part that is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring. A metallic oxide is formed in at least one of the first wiring and the second wiring.

Abstract translation: 公开了一种半导体装置，电子装置和半导体装置的制造方法。 在一个示例中，半导体装置包括第一半导体部分，其包括第一布线，第二半导体部分粘附到第一半导体部分，并且包括电连接到第一布线的第二布线。 金属氧化物形成在第一布线和第二布线中的至少一个中。

公开(公告)号：US20180247913A1

公开(公告)日：2018-08-30

申请号：US15444130

申请日：2017-02-27

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC. ,  NATIONAL CHUNG HSING UNIVERSITY

Inventor： Ying-Ta CHIU ,  Shang-Kun HUANG ,  Yong-Da CHIU ,  Jenn-Ming SONG

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/05 ,  H01L2224/80009 ,  H01L2224/80092 ,  H01L2224/8012 ,  H01L2224/80203

Abstract: The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a first metal contact and a second electronic component including a second metal contact, changing a lattice of the first metal contact, and bonding the first metal contact to the second metal contact under a predetermined pressure and a predetermined temperature.

公开(公告)号：US09379006B2

公开(公告)日：2016-06-28

申请号：US14162140

申请日：2014-01-23

Applicant: Sony Corporation

Inventor： Yoshihisa Kagawa ,  Naoki Komai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L21/76838 ,  H01L23/53209 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03505 ,  H01L2224/03616 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2224/80004 ,  H01L2224/80011 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: A semiconductor apparatus, electronic device, and method of manufacturing the semiconductor apparatus are disclosed. In one example, the semiconductor apparatus comprises a first semiconductor part that includes a first wiring, and a second semiconductor part that is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring. A metallic oxide is formed in at least one of the first wiring and the second wiring.

Abstract translation: 公开了一种半导体装置，电子装置和半导体装置的制造方法。 在一个示例中，半导体装置包括第一半导体部分，其包括第一布线，第二半导体部分粘附到第一半导体部分，并且包括电连接到第一布线的第二布线。 金属氧化物形成在第一布线和第二布线中的至少一个中。

公开(公告)号：US08497148B2

公开(公告)日：2013-07-30

申请号：US13189057

申请日：2011-07-22

Applicant: Bruce C. S. Chou

Inventor： Bruce C. S. Chou

IPC: H01L21/58 ,  H01L23/48

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。

公开(公告)号：US20120241961A1

公开(公告)日：2012-09-27

申请号：US13416412

申请日：2012-03-09

Applicant: Yoshihisa Kagawa ,  Naoki Komai

Inventor： Yoshihisa Kagawa ,  Naoki Komai

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76838 ,  H01L23/53209 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03505 ,  H01L2224/03616 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2224/80004 ,  H01L2224/80011 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: Disclosed herein is a semiconductor apparatus including: a first semiconductor part including a first wiring; a second semiconductor part which is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring; and a metallic oxide formed by a reaction between oxygen and a metallic material which reacts with oxygen more easily than hydrogen does, the metallic oxide having been diffused into a region which includes a joint interface between the first wiring and the second wiring and the inside of at least one of the first wiring and the second wiring.

Abstract translation: 本发明公开了一种半导体装置，包括：第一半导体部件，包括第一布线; 第二半导体部分，其粘附到第一半导体部分，并且包括电连接到第一布线的第二布线; 以及通过氧与金之间的反应比金更容易地与氧反应形成的金属氧化物，所述金属氧化物已经扩散到包括第一布线和第二布线之间的接合界面的区域中，以及内部 第一布线和第二布线中的至少一个。