公开(公告)号：US20170221705A1

公开(公告)日：2017-08-03

申请号：US15233734

申请日：2016-08-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Mie MATSUO ,  Atsuko KAWASAKI

IPC: H01L21/02 ,  H01L21/762 ,  H01L23/373

CPC classification number: H01L21/02529 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/76256 ,  H01L23/3738 ,  H01L29/2003 ,  H01L29/66446 ,  H01L33/007

Abstract: According to one embodiment, a semiconductor device is provided with a first single crystal layer, a polycrystalline layer provided on an entire surface of the first single crystal layer, and a second single crystal layer bonded to the polycrystalline layer. The coefficient of thermal expansion of the polycrystalline layer is greater than the coefficient of thermal expansion of the second single crystal layer, and is smaller than the coefficient of thermal expansion of a compound semiconductor layer which can be provided on the second single crystal layer using an intervening a buffer layer.

公开(公告)号：US20160013099A1

公开(公告)日：2016-01-14

申请号：US14718435

申请日：2015-05-21

Applicant: Kabushiki Kaisha Toshiba

Inventor： Kazumasa TANIDA ,  Takamitsu YOSHIDA ,  Kuniaki UTSUMI ,  Atsuko KAWASAKI

IPC: H01L21/768 ,  H01L25/065 ,  H01L21/283 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/4853 ,  H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14643 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/03831 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/08059 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80365 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00 ,  H01L2924/00014

Abstract: According to embodiments, a semiconductor device is provided. The semiconductor device includes an insulation layer, an electrode, and a groove. The insulation layer is provided on a surface of a substrate. The electrode is buried in the insulation layer, and a first end surface of the electrode is exposed from the insulation layer. The groove is formed around the electrode on the surface of the substrate. The groove has an outside surface of the electrode as one side surface, and the groove is opened on the surface side of the insulation layer. The first end surface of the electrode buried in the insulation layer protrudes from the surface of the insulation layer.

Abstract translation: 根据实施例，提供一种半导体器件。 半导体器件包括绝缘层，电极和沟槽。 绝缘层设置在基板的表面上。 电极被埋在绝缘层中，电极的第一端面从绝缘层露出。 在基板表面上的电极周围形成凹槽。 凹槽具有作为一个侧面的电极的外表面，并且在绝缘层的表面侧上开槽。 埋在绝缘层中的电极的第一端面从绝缘层的表面突出。

公开(公告)号：US20160343682A1

公开(公告)日：2016-11-24

申请号：US15230125

申请日：2016-08-05

Applicant: Kabushiki Kaisha Toshiba

Inventor： Atsuko KAWASAKI

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08111 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/215 ,  H01L2224/24146 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/80001

Abstract: Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

Abstract translation: 某些实施例提供一种用于制造半导体器件的方法，包括形成第一互连层，该第一互连层具有从第一互连层的表面露出的第一导电层和第一绝缘层，形成具有第二导电层的第二互连层和 第二绝缘层，其从第二互连层的表面露出，通过使第一绝缘层的表面的部分区域低于第一绝缘层的表面，在第一绝缘层的表面上形成第一非接合表面 导电层，所述部分区域包含所述第一导电层的周围环境，并且连接所述第一导电层的表面和所述第二导电层的表面，并且将除了所述第一非接合表面和所述表面之外的所述第一绝缘层的表面 的第二绝缘层。

公开(公告)号：US20160172401A1

公开(公告)日：2016-06-16

申请号：US14958214

申请日：2015-12-03

Applicant: Kabushiki Kaisha Toshiba

Inventor： Atsuko KAWASAKI ,  Soichiro Ueno

IPC: H01L27/146 ,  H04N5/335 ,  H04N5/363 ,  H04N5/225

CPC classification number: H01L27/14627 ,  H01L27/14623 ,  H01L27/14685 ,  H04N5/2257

Abstract: Certain embodiments provide a solid-state imaging device including a sensor substrate including a microlens, a transparent resin layer provided so as to be in contact with a main surface of the sensor substrate including a surface of the microlens, and a transparent substrate disposed on a top surface of the transparent resin layer. A thermal conductivity of the transparent resin layer is higher than that of air, and a refractive index of the transparent resin layer is lower than that of the microlens and is equal to or lower than that of the transparent substrate.

Abstract translation: 某些实施例提供一种固态成像装置，其包括：传感器基板，包括微透镜，透明树脂层，设置成与包括微透镜的表面的传感器基板的主表面接触;以及透明基板， 透明树脂层的顶面。 透明树脂层的导热率高于空气，并且透明树脂层的折射率低于微透镜的折射率，并且等于或低于透明树脂层的折射率。

公开(公告)号：US20150162294A1

公开(公告)日：2015-06-11

申请号：US14518389

申请日：2014-10-20

Applicant: Kabushiki Kaisha Toshiba

Inventor： Atsuko KAWASAKI

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/24 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/215 ,  H01L2224/24146 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/80001

Abstract: Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

Abstract translation: 某些实施例提供一种用于制造半导体器件的方法，包括形成第一互连层，该第一互连层具有从第一互连层的表面露出的第一导电层和第一绝缘层，形成具有第二导电层的第二互连层和 第二绝缘层，其从第二互连层的表面露出，通过使第一绝缘层的表面的部分区域低于第一绝缘层的表面，在第一绝缘层的表面上形成第一非接合表面 导电层，所述部分区域包含所述第一导电层的周围环境，并且连接所述第一导电层的表面和所述第二导电层的表面，并且将除了所述第一非接合表面和所述表面之外的所述第一绝缘层的表面 的第二绝缘层。