公开(公告)号：US20190237419A1

公开(公告)日：2019-08-01

申请号：US16383455

申请日：2019-04-12

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Paul M. ENQUIST

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/50 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/036 ,  H01L2224/03616 ,  H01L2224/03825 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05561 ,  H01L2224/05562 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08112 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/80031 ,  H01L2224/80035 ,  H01L2224/80047 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/8019 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2224/29339 ,  H01L2224/29386 ,  H01L2924/053 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/049 ,  H01L2924/01014 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/051 ,  H01L2924/042

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：US20180033752A1

公开(公告)日：2018-02-01

申请号：US15730174

申请日：2017-10-11

Applicant: Infineon Technologies AG

Inventor： Swee Kah Lee ,  Hock Heng Chong ,  Mei Chin Ng ,  Aileen Manantan Soriano ,  Fong Mei Lum ,  Muhammad Muhammat Sanusi ,  Soon Lock Goh

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/683 ,  H01L23/495 ,  H01L21/78

CPC classification number: H01L24/06 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/03 ,  H01L2224/0381 ,  H01L2224/03825 ,  H01L2224/05655 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

公开(公告)号：US09716066B2

公开(公告)日：2017-07-25

申请号：US14779022

申请日：2013-06-29

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  James Y. Jeong ,  Hsiao-Kang Chang ,  John Muirhead ,  Adwait Telang ,  Puneesh Puri ,  Jiho Kang ,  Nitin M. Patel

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/116 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014

Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

公开(公告)号：US09595651B2

公开(公告)日：2017-03-14

申请号：US14422990

申请日：2013-12-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshihisa Yamashita ,  Seiichi Nakatani ,  Koji Kawakita ,  Susumu Sawada

IPC: H01L23/02 ,  H01L21/00 ,  H01L33/64 ,  H01L33/58 ,  H01L33/62 ,  H01L33/56 ,  C23C14/34 ,  C23C14/58 ,  H01L21/768

CPC classification number: H01L33/647 ,  C23C14/34 ,  C23C14/5846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3735 ,  H01L24/19 ,  H01L24/97 ,  H01L25/167 ,  H01L33/52 ,  H01L33/56 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/0346 ,  H01L2224/03825 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8203 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for manufacturing an electronic component package comprises: (i) preparing a metal foil having opposed principal surface “A” for placement of an electronic component and principal surface “B”, and a through-hole located in an electronic component-placement region of surface “A”; (ii) placing the electronic component on the metal foil such that the electronic component is positioned in the electronic component-placement region, and an opening of the through-hole is capped with an electrode of the electronic component; (iii) forming a sealing resin layer on surface “A” such that the electronic component is covered with the sealing resin layer; and (iv) forming a metal plating layer on surface “B”. A dry plating process and a wet plating process are performed to form the metal plating layer in step (iv) such that the through-hole is filled with the metal plating layer, and the metal foil and the metal plating layer are integrated.

Abstract translation: 一种电子部件封装的制造方法，其特征在于，具备：（i）制作具有相对的主面“A”用于配置电子部件和主面“B”的金属箔，以及位于电子部件配置区域 表面“A”; （ii）将电子部件放置在金属箔上使得电子部件位于电子部件放置区域中，并且通孔的开口用电子部件的电极封盖; （iii）在表面“A”上形成密封树脂层，使得电子部件被密封树脂​​层覆盖; 和（iv）在表面“B”上形成金属镀层。 在步骤（iv）中进行干电镀处理和湿式电镀处理以形成金属镀层，使得通孔填充有金属镀层，并且金属箔和金属镀层一体化。

公开(公告)号：US20150228603A1

公开(公告)日：2015-08-13

申请号：US14684103

申请日：2015-04-10

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

Abstract translation: 一些实施例包括平面化方法。 衬套跨越半导体衬底并沿着从衬底向上延伸的柱形成。 有机填充材料形成在衬里上和柱之间。 形成平面化的表面，该平面化表面延伸穿过柱并穿过衬套和填充材料中的一个或两个。 一些实施例包括包含半导体管芯的半导体结构。 导电柱延伸穿过模具。 柱具有在模具的背面上方的上表面，并且具有在背面和上表面之间延伸的侧壁表面。 衬套穿过模具的后表面并且沿着柱的侧壁表面。 导电盖在柱的上表面之上，并且沿着邻近柱的侧壁表面的衬垫具有边缘。

公开(公告)号：US20110233782A1

公开(公告)日：2011-09-29

申请号：US13052769

申请日：2011-03-21

Applicant: Shu-Ming CHANG ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

Inventor： Shu-Ming CHANG ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L33/62 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03825 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92142 ,  H01L2224/92143 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/1182 ,  H01L2224/03 ,  H01L2224/0382 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.

Abstract translation: 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片，其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。

公开(公告)号：US20110114707A1

公开(公告)日：2011-05-19

申请号：US12592134

申请日：2009-11-19

Applicant: Gregory P. Matis

Inventor： Gregory P. Matis

IPC: B23K1/20 ,  B05D3/10 ,  C25D5/00

CPC classification number: C25D5/48 ,  B23K1/0016 ,  B23K2101/40 ,  B32B15/01 ,  C22C28/00 ,  C25D5/34 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03825 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05563 ,  H01L2224/05582 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/26145 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/27436 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/75501 ,  H01L2224/83193 ,  H01L2224/83815 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method for making thermally conductive high aspect ratio large area contact between devices with different coefficients of thermal expansion. The method of the invention includes the creation or placement of sparse structures on at least one of two surfaces or between the surfaces to maintain enough thickness that an interposed bonding material remains sufficiently compliant that relative thermal motion of the two devices can occur without damage to the devices or the bond during changes in temperature.

Abstract translation: 在具有不同热膨胀系数的器件之间制造导热高纵横比大面积接触的方法。 本发明的方法包括在两个表面中或两个表面之间的至少一个表面上创建或放置稀疏结构，以保持足够的厚度，使插入的粘合材料保持足够的柔顺性，使两个装置的相对热运动可以发生而不会损坏 设备或温度变化时的粘合。

公开(公告)号：US09324674B2

公开(公告)日：2016-04-26

申请号：US14562129

申请日：2014-12-05

Applicant: NXP B.V.

Inventor： Johannes Wilhelmus van Rijckevorsel ,  Emiel de Bruin

IPC: H01L23/482 ,  H01L23/00 ,  H01L23/66

CPC classification number: H01L24/29 ,  H01L23/4827 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L2223/6644 ,  H01L2224/03825 ,  H01L2224/03826 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/27464 ,  H01L2224/29084 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/32502 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83444 ,  H01L2224/83805 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1421 ,  H01L2924/15747 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01014

Abstract: A die comprising a body of semiconductor material, said body configured to receive a solder layer of gold containing alloy for use in die bonding said die to a substrate, wherein the die includes an interface layer on a surface of the body for receiving the solder layer, the interface layer having a plurality of sub-layers of different metals.

Abstract translation: 一种包括半导体材料体的芯片，所述主体被配置为接收用于将所述裸片接合到基板的用于将所述裸片接合的含金合金的焊料层，其中所述管芯包括在所述主体的表面上用于接纳焊料层的界面层 ，界面层具有多个不同金属的子层。

公开(公告)号：US20160086914A1

公开(公告)日：2016-03-24

申请号：US14958183

申请日：2015-12-03

Applicant: International Business Machines Corporation

Inventor： Tien-Jen Cheng ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/488 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0346 ,  H01L2224/03464 ,  H01L2224/038 ,  H01L2224/03825 ,  H01L2224/03829 ,  H01L2224/039 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/27464 ,  H01L2224/27831 ,  H01L2224/32145 ,  H01L2224/32146 ,  H01L2224/80203 ,  H01L2224/80447 ,  H01L2224/80895 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/1011 ,  H01L2924/3511 ,  H01L2224/80 ,  H01L2224/05155 ,  H01L2924/00012 ,  H01L2924/01046 ,  H01L2224/03616 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2224/05552

Abstract: The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

公开(公告)号：US09029257B2

公开(公告)日：2015-05-12

申请号：US13952481

申请日：2013-07-26

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

Abstract translation: 一些实施例包括平面化方法。 衬套跨越半导体衬底并沿着从衬底向上延伸的柱形成。 有机填充材料形成在衬里上和柱之间。 形成平面化的表面，该平面化表面延伸穿过柱并穿过衬套和填充材料中的一个或两个。 一些实施例包括包含半导体管芯的半导体结构。 导电柱延伸穿过模具。 柱具有在模具的背面上方的上表面，并且具有在背面和上表面之间延伸的侧壁表面。 衬套穿过模具的后表面并且沿着柱的侧壁表面。 导电盖在柱的上表面之上，并且沿着邻近柱的侧壁表面的衬垫具有边缘。