Invention Grant
- Patent Title: Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias
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Application No.: US14779022Application Date: 2013-06-29
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Publication No.: US09716066B2Publication Date: 2017-07-25
- Inventor: Kevin J. Lee , James Y. Jeong , Hsiao-Kang Chang , John Muirhead , Adwait Telang , Puneesh Puri , Jiho Kang , Nitin M. Patel
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- International Application: PCT/US2013/048792 WO 20130629
- International Announcement: WO2014/209404 WO 20141231
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/768 ; H01L23/48 ; H01L23/31 ; H01L23/00 ; H01L21/683
Abstract:
A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
Public/Granted literature
- US20160049371A1 INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS Public/Granted day:2016-02-18
Information query
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