公开(公告)号：US09960134B2

公开(公告)日：2018-05-01

申请号：US15269212

申请日：2016-09-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Li Hsiao ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chih-Hang Tung ,  Cheng-Chang Wei

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L21/44 ,  H01L23/52

CPC分类号： H01L24/11 ,  H01L21/44 ,  H01L21/76885 ,  H01L23/49811 ,  H01L23/52 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/13018 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/80815 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.

公开(公告)号：US20180047709A1

公开(公告)日：2018-02-15

申请号：US15793325

申请日：2017-10-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Ming-Da Cheng

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/038 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05693 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1358 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48693 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48793 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48893 ,  H01L2224/73204 ,  H01L2224/81009 ,  H01L2224/81026 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/01006

摘要： Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

公开(公告)号：US09881900B2

公开(公告)日：2018-01-30

申请号：US15379437

申请日：2016-12-14

申请人： ROHM CO., LTD.

发明人： Hirofumi Takeda ,  Yoshihisa Takada

IPC分类号： H01L23/24 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L25/0652 ,  G01C17/30 ,  H01L23/13 ,  H01L23/147 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/11618 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13566 ,  H01L2224/13583 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/10158 ,  H01L2924/15156 ,  H01L2924/15157 ,  H01L2924/15321 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00012

摘要： A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).

公开(公告)号：US09704943B2

公开(公告)日：2017-07-11

申请号：US14462490

申请日：2014-08-18

申请人： XINTEC INC.

发明人： Wei-Ming Lai ,  Yu-Wen Hu

IPC分类号： H01L27/08 ,  H01L49/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/64 ,  H01L23/532

CPC分类号： H01L28/10 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11825 ,  H01L2224/11903 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1355 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/1206

摘要： A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed.

公开(公告)号：US20160351520A1

公开(公告)日：2016-12-01

申请号：US14944054

申请日：2015-11-17

申请人： Monolithic Power Systems, Inc.

发明人： Hunt Hang JIANG

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03825 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11848 ,  H01L2224/11901 ,  H01L2224/13007 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/16245 ,  H01L2224/80801 ,  H01L2224/80815 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047

摘要： An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer.

摘要翻译： 集成电路（IC）芯片包括在表面上具有金属间涂层的铜结构。 IC芯片包括具有集成电路的基板。 金属焊盘电连接到集成电路。 铜结构电连接到金属垫。 焊料凸块设置在铜结构上。 铜结构的表面具有金属间化合物的涂层。 铜结构可以是再分布层和布置在再分布层上的铜柱。

公开(公告)号：US20160343692A1

公开(公告)日：2016-11-24

申请号：US15230921

申请日：2016-08-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/0273 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/1131 ,  H01L2224/11424 ,  H01L2224/1152 ,  H01L2224/1162 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00014 ,  H01L2924/00

摘要： A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

公开(公告)号：US09449913B2

公开(公告)日：2016-09-20

申请号：US13994668

申请日：2011-10-28

申请人： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

发明人： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

IPC分类号： H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/29 ,  H01L23/00

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/291 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/0105 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

摘要： A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

摘要翻译： 描述了三维互连结构和制造方法，其中金属再分配层（RDL）与硅通孔（TSV）集成并且使用单个镶嵌型工艺流程。 氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。

公开(公告)号：US20160155684A1

公开(公告)日：2016-06-02

申请号：US15014929

申请日：2016-02-03

申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

发明人： CHANG-MING LIN ,  YU-JUAN TAO

IPC分类号： H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/485 ,  H01L21/28 ,  H01L21/28587 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/48 ,  H01L23/482 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06102 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11903 ,  H01L2224/1191 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/14051 ,  H01L2224/16055 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17106 ,  H01L2224/17519 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/831 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L21/304 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

摘要： A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface, and an electroplating seed layer on the first surface of the semiconductor substrate. The method also includes forming a plurality of columnar electrodes over the electroplating seed layer, where the columnar electrodes include first columnar electrodes and second columnar electrodes. Further, the method includes forming a diffusion barrier layer over the first columnar electrodes and the second columnar electrodes, forming a plurality of first solder balls over the diffusion barrier layer on the first columnar electrodes. The method also includes providing a packaging substrate having solder terminals corresponding to the first solder balls, and mounting the semiconductor substrate onto the packaging substrate in a flipped position, such that the first solder balls are connected with the solder terminals.

摘要翻译： 提供半导体封装方法。 该方法包括提供半导体衬底。 半导体衬底具有第一表面和第二表面，以及在半导体衬底的第一表面上的电镀籽晶层。 该方法还包括在电镀种子层上形成多个柱状电极，其中柱状电极包括第一柱状电极和第二柱状电极。 此外，该方法包括在第一柱状电极和第二柱状电极上形成扩散阻挡层，在第一柱状电极上的扩散阻挡层上形成多个第一焊球。 该方法还包括提供具有对应于第一焊球的焊接端子的封装基板，并将半导体基板安装在翻转位置的封装基板上，使得第一焊球与焊接端子连接。

公开(公告)号：US20160049371A1

公开(公告)日：2016-02-18

申请号：US14779022

申请日：2013-06-29

申请人： INTEL CORPORATION

发明人： Kevin J. Lee ,  James Y. Jeong ,  Hsiao-Kang Chang ,  John Muirhead ,  Adwait Telang ,  Puneesh Puri ,  Jiho Kang ,  Nitin M. Patel

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/5384 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/116 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014

摘要： A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

摘要翻译： 描述了三维互连结构和制造方法，其中金属再分布层（RDL）与硅通孔（TSV）集成并且使用“平板通过抗蚀剂”型工艺流程。 氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。

公开(公告)号：US20160020195A1

公开(公告)日：2016-01-21

申请号：US14616013

申请日：2015-02-06

申请人： Siliconware Pricision Industries Co., Ltd.

发明人： Cheng-Chia Chiang ,  Hsin-Ta Lin ,  Fu-Tang Huang ,  Yu-Po Wang ,  Lung-Yuan Wang ,  Chu-Chi Hsu ,  Chia-Kai Shih

IPC分类号： H01L25/16 ,  H01L23/31 ,  H01L23/42 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/162 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/562 ,  H01L23/564 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05016 ,  H01L2224/05078 ,  H01L2224/0519 ,  H01L2224/05561 ,  H01L2224/05582 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/06132 ,  H01L2224/06181 ,  H01L2224/11825 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/13671 ,  H01L2224/1369 ,  H01L2224/1401 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/0635 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/00

摘要： A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

摘要翻译： 提供一种半导体封装，其包括：第一半导体器件，其具有第一顶表面和与第一顶表面相对的第一底表面; 形成在所述第一半导体器件的所述第一顶表面上的多个导电球; 具有第二顶表面和与第二顶表面相对的第二底表面的第二半导体器件; 以及形成在所述第二半导体器件的所述第二底表面上并相应地接合到所述导电球以用于电连接所述第一半导体器件和所述第二半导体器件的多个导电柱，其中所述导电柱的高度小于300μm。 因此，本发明可以容易地控制半导体封装的高度，并且可应用于具有细间距导电球的半导体封装。