公开(公告)号：US20240145420A1

公开(公告)日：2024-05-02

申请号：US17975654

申请日：2022-10-28

申请人： Intel Corporation

发明人： Bok Eng CHEAH ,  Seok Ling LIM ,  Kooi Chi OOI ,  Jackson Chung Peng KONG ,  Jenny Shio Yin ONG

IPC分类号： H01L23/00

CPC分类号： H01L24/26 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/13101 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13188 ,  H01L2224/1413 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/2732 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/30051 ,  H01L2224/3016 ,  H01L2224/32227 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83007 ,  H01L2224/831 ,  H01L2224/83193 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/01087 ,  H01L2924/0133 ,  H01L2924/0543 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/1432 ,  H01L2924/1434

摘要： The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.

公开(公告)号：US11823988B2

公开(公告)日：2023-11-21

申请号：US17913705

申请日：2021-02-26

申请人： Siemens Aktiengesellschaft

发明人： Matthias Nährig ,  Jens Schmenger

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49811 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/32111 ,  H01L2224/48091 ,  H01L2224/831

摘要： A semiconductor module includes a housing, a pin arranged in the housing and including a first contact region which has a press-fit connection, a semiconductor component arranged in the housing and electrically conductively connected to the pin, and a first substrate arranged in the housing and clamped in the housing via the pin by a non-positive locking connection, which, when formed, causes the press-fit connection to be deformed elastically and/or plastically with the first substrate. The first substrate has a first recess which is open and at least in part encompasses the pin in the first contact region. A metallic coating is applied to the first substrate at least in a region of the first recess so as to electrically conductively connect the first substrate to the semiconductor component, and a second substrate is in contact with the pin and connected within the housing in a non-releasable manner.

公开(公告)号：US20230369274A1

公开(公告)日：2023-11-16

申请号：US17813639

申请日：2022-07-20

申请人： Taiwan Semiconduction Manufacturing Co., Ltd.

发明人： Jiun Yi Wu ,  Chen-Hua Yu

IPC分类号： H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  G02B6/42

CPC分类号： H01L24/26 ,  H01L25/105 ,  H01L23/3185 ,  H01L25/50 ,  H01L24/32 ,  H01L24/16 ,  H01L24/73 ,  H01L24/20 ,  H01L23/13 ,  H01L23/5386 ,  H01L24/92 ,  G02B6/4268 ,  G02B6/4253 ,  H01L24/19 ,  H01L2224/19 ,  H01L24/13 ,  H01L2224/13082 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/26175 ,  H01L2224/32237 ,  H01L2224/32137 ,  H01L2224/73204 ,  H01L23/5383 ,  H01L2224/92125 ,  H01L24/81 ,  H01L2224/81815 ,  H01L24/83 ,  H01L2224/831 ,  H01L2224/83855

摘要： A package includes a package substrate including an insulating layer having a trench and a package component bonded to the package substrate. The package component includes a redistribution structure, an optical die bonded to the redistribution structure, the optical die including an edge coupler near a first sidewall of the optical die, a dam structure on the redistribution structure near the first sidewall of the optical die, a first underfill between the optical die and the redistribution structure, an encapsulant encapsulating the optical die, and an optical glue in physical contact with the first sidewall of the optical die. The first underfill does not extend along the first sidewall of the optical die. The optical glue separates the dam structure from the encapsulant. The package further includes a second underfill between the insulating layer and the package component. The second underfill is partially disposed in the trench.

公开(公告)号：US20190252346A1

公开(公告)日：2019-08-15

申请号：US16390159

申请日：2019-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Tien-I Bao

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/8192 ,  H01L2224/831 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps.

公开(公告)号：US20180261563A1

公开(公告)日：2018-09-13

申请号：US15975232

申请日：2018-05-09

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Lu-Yi Chen

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/525 ,  H01L23/498 ,  H01L23/48 ,  H01L23/367 ,  H01L23/14 ,  H01L21/768 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/211 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/82101 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/831 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/922 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/19 ,  H01L2924/00

摘要： A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

公开(公告)号：US20180226273A1

公开(公告)日：2018-08-09

申请号：US15885780

申请日：2018-01-31

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Robert Francis DARVEAUX ,  Bruce Joseph FREYMAN ,  Yi LIU

IPC分类号： H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L23/29

CPC分类号： H01L21/563 ,  H01L21/0274 ,  H01L21/268 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4864 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/54486 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83002 ,  H01L2224/83007 ,  H01L2224/831 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/0665 ,  H01L2924/1421 ,  H01L2924/19011 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00

摘要： Described herein are methods of manufacturing dual-sided packaged electronic modules to control the distribution of an under-fill material between one or more components and a packaging substrate. The disclosed technologies include using a dam on a packaging substrate that is configured to prevent or limit the flow of a capillary under-fill material. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array. Accordingly, the disclosed technologies control under-fill for dual-sided ball grid array packages using a dam on a packaging substrate.

公开(公告)号：US09972591B2

公开(公告)日：2018-05-15

申请号：US15419069

申请日：2017-01-30

申请人： Renesas Electronics Corporation

发明人： Hideki Harano

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/11 ,  H01L21/563 ,  H01L23/3142 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/14131 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/00

摘要： To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a semiconductor substrate having an insulating film in which an opening that exposes each of a plurality of electrode pads is formed is provided, and a flux member including conductive particles is arranged over each of the electrode pads. Thereafter, a solder ball is arranged over each of the electrode pads via the flux member, and is then heated via the flux member so that the solder ball is bonded to each of the electrode pads. The width of the opening of the insulating film is smaller than the width (diameter) of the solder ball.

公开(公告)号：US09929124B2

公开(公告)日：2018-03-27

申请号：US15317686

申请日：2014-06-26

申请人： EV GROUP E. THALLNER GMBH

发明人： Jurgen Burggraf

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00 ,  C03C27/10 ,  C09J5/00 ,  C23C14/58

CPC分类号： H01L24/83 ,  C03C27/10 ,  C09J5/00 ,  C09J2400/143 ,  C23C14/5826 ,  H01L24/03 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/743 ,  H01L2224/038 ,  H01L2224/04026 ,  H01L2224/2731 ,  H01L2224/27318 ,  H01L2224/27416 ,  H01L2224/27418 ,  H01L2224/29015 ,  H01L2224/29017 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/2939 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/83022 ,  H01L2224/83048 ,  H01L2224/831 ,  H01L2224/83102 ,  H01L2224/83121 ,  H01L2224/83143 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83862 ,  H01L2224/83868 ,  H01L2224/83871 ,  H01L2224/83874 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A method for bonding a first substrate with a second substrate by means of a connecting layer that is arranged between the substrates and that is comprised of a connecting material with the following steps: applying the connecting material to the first substrate and/or the second substrate in liquid form, and distributing the connecting material between the substrates by bringing the substrates closer and as a result forming the shape of the connecting layer with a thickness t.

公开(公告)号：US09824991B2

公开(公告)日：2017-11-21

申请号：US15421340

申请日：2017-01-31

申请人： INTEL CORPORATION

发明人： Aleksandar Aleksov ,  Tony Dambrauskas ,  Danish Faruqui ,  Mark S. Hlad ,  Edward R. Prack

IPC分类号： H01L21/58 ,  H01L23/00 ,  H01L21/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/02118 ,  H01L21/02263 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/3205 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76883 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3142 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81026 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81375 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81913 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.

公开(公告)号：US20170098607A1

公开(公告)日：2017-04-06

申请号：US15378622

申请日：2016-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Yu Lu ,  Hsien-Pin Hu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Tzuan-Horng Liu ,  Shih-Wen Huang ,  Chun Hua Chang

IPC分类号： H01L23/525 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/5256 ,  H01L21/4846 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/56 ,  H01L21/304 ,  H01L21/78

摘要： Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.