公开(公告)号：US08487419B2

公开(公告)日：2013-07-16

申请号：US13347898

申请日：2012-01-11

Applicant: Takashi Katsuki

Inventor： Takashi Katsuki

IPC: H01L23/495

CPC classification number: H01L24/92 ,  F02P3/0453 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49589 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48755 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/85455 ,  H01L2224/92 ,  H01L2224/922 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85

Abstract: A method of manufacturing a semiconductor apparatus according to aspects of the invention can include the steps of coating solder on an predetermined area in the upper surface of a lead frame, mounting a chip on solder and melting solder with a hot plate for bonding the chip to the lead frame. The method can also include wiring with bonding wires, turning lead frame upside down, placing lead frame turned upside down on heating cradle, coating solder, the melting point of which is lower than the solder melting point and mounting electronic part on solder; and melting solder with heating cradle for bonding electronic part to lead frame. The bonding with solder can be conducted at a high ambient temperature. Aspects of the semiconductor apparatus can facilitate mounting semiconductor devices and electronic parts on both surfaces of a lead frame divided to form wiring circuits without through complicated manufacturing steps.

Abstract translation: 根据本发明的方面的半导体装置的制造方法可以包括以下步骤：在引线框架的上表面的预定区域上涂覆焊料，将芯片安装在焊料上并用焊盘熔化焊料，以将芯片接合到 引线框架。 该方法还可以包括使用接合线布线，将引线框倒置，将引线框倒置在加热托架上，涂层焊料熔点低于焊料熔点，并将电子部件安装在焊料上; 并用加热支架熔化焊料，用于将电子部件接合到引线框架。 与焊料的接合可以在高环境温度下进行。 半导体装置的方面可以有助于在引导框架的两个表面上安装半导体装置和电子部件，以分离形成布线电路，而无需通过复杂的制造步骤。

公开(公告)号：US20110074012A1

公开(公告)日：2011-03-31

申请号：US12923579

申请日：2010-09-28

Applicant: Masanori Itoh

Inventor： Masanori Itoh

IPC: H01L23/66

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L23/053 ,  H01L23/10 ,  H01L23/18 ,  H01L23/3121 ,  H01L24/06 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/17135 ,  H01L2224/17164 ,  H01L2224/17517 ,  H01L2224/29007 ,  H01L2224/29013 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/8114 ,  H01L2224/81192 ,  H01L2224/83192 ,  H01L2224/922 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: There is provided a substrate with a built-in semiconductor element, including: a first substrate at which a wiring layer is layered on a dielectric layer; a semiconductor element that is structured to include a distributed constant circuit, and at which plural bonding pads are formed at a peripheral region of a surface that faces the first substrate, and that is electrically connected to the wiring layer by an electrically-conductive member that has electrical conductivity and corresponds to the plural bonding pads; a supporting member that is disposed at an inner side region that is further toward an inner side than the peripheral region of the semiconductor element, and that is interposed between the semiconductor element and the first substrate and supports the semiconductor element; and a second substrate that is laminated to the first substrate and the semiconductor element.

Abstract translation: 提供了具有内置半导体元件的基板，包括：布线层在其上层叠在电介质层上的第一基板; 构造成包括分布常数电路的半导体元件，并且在面对第一基板的表面的周边区域形成有多个接合焊盘，并且通过导电构件电连接到布线层， 具有导电性并对应于多个键合焊盘; 支撑构件，其设置在比半导体元件的周边区域更靠内侧的内侧区域，并且设置在所述半导体元件和所述第一基板之间并支撑所述半导体元件; 以及层叠到第一基板和半导体元件的第二基板。

公开(公告)号：US09997481B2

公开(公告)日：2018-06-12

申请号：US13628549

申请日：2012-09-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/367 ,  H01L23/525 ,  H01L21/768 ,  H01L23/48 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/211 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/831 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/922 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

公开(公告)号：US20160181174A1

公开(公告)日：2016-06-23

申请号：US14802341

申请日：2015-07-17

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sudeep Mandal ,  Sebastian T. Ventrone

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/367 ,  H01L21/4871 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/922 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2924/00012 ,  H01L2924/04941

Abstract: A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.

Abstract translation: 公开了一种由半导体材料制造的芯片，其可以包括位于从芯片背面的第一深度以下的有源器件，以及将热量从有源器件移除到芯片背面的结构。 该结构可以包括导热部分通孔（TCPV），其可以包括从芯片背侧朝向有源器件的深度的凹陷小于第一深度。 每个TCPV可以包括沉积在凹槽内并沉积在芯片背面的阻挡层。 每个TCPV还可以包括沉积在阻挡层上的导热层。 该结构还可以包括电连接到有源器件的穿硅通孔（TSV），其从芯片的背面延伸到有源器件侧，以将热量从有源器件导电移除到芯片的背面。

公开(公告)号：US20180261563A1

公开(公告)日：2018-09-13

申请号：US15975232

申请日：2018-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/525 ,  H01L23/498 ,  H01L23/48 ,  H01L23/367 ,  H01L23/14 ,  H01L21/768 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/211 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/82101 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/831 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/922 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/19 ,  H01L2924/00

Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

公开(公告)号：US09184112B1

公开(公告)日：2015-11-10

申请号：US14572950

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sudeep Mandal ,  Sebastian T. Ventrone

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/367 ,  H01L23/58 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L23/3171 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49827 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5384 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/922 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2924/00012

Abstract: A chip fabricated from a semiconductor material is disclosed. The chip may include active devices located below a first depth from a chip back side and a structure configured to remove heat from the chip. The structure may include microvias electrically insulated from the active devices and having a second depth, less than the first depth, from the back side towards the active devices. Each microvia may also have a fill material having a thermal conductivity greater than a semiconductor thermal conductivity. The structure may also include thermally conductive material regions on the back side of the chip in contact with sets of microvias. The structure may also include through-silicon vias electrically connected to the active devices, and extending from the back side to an active device side of the chip and configured to remove heat from the active devices to the back side of the chip.

Abstract translation: 公开了一种由半导体材料制成的芯片。 芯片可以包括位于从芯片背面的第一深度下方的有源器件和被配置为从芯片去除热量的结构。 该结构可以包括与有源器件电绝缘并且具有小于第一深度的从背侧朝向有源器件的第二深度的微孔。 每个微孔也可以具有导热率大于半导体热导率的填充材料。 该结构还可以包括在芯片的背面上与微孔组接触的导热材料区域。 该结构还可以包括电连接到有源器件的穿硅通孔，并且从芯片的背面延伸到有源器件侧并且被配置为将热量从有源器件移除到芯片的背面。

公开(公告)号：US20130299961A1

公开(公告)日：2013-11-14

申请号：US13628549

申请日：2012-09-27

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Lu-Yi Chen

IPC: H01L21/56 ,  H01L23/34

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/211 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/831 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/922 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

Abstract translation: 半导体封装包括堆积结构; 以倒装芯片方式布置在积层结构上并具有穿过其的多个凸块的半导体; 设置在所述半导体芯片上的电子元件; 以及密封剂，其形成在积聚结构上并封装半导体芯片和电子元件，从而提高产品产量和整体散热效率。

公开(公告)号：US09666557B2

公开(公告)日：2017-05-30

申请号：US13905194

申请日：2013-05-30

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/00 ,  H01L23/051 ,  H01L23/36 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L25/065 ,  H01L23/051 ,  H01L23/34 ,  H01L23/36 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/04 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/08237 ,  H01L2224/08257 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/30181 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73151 ,  H01L2224/73251 ,  H01L2224/80898 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/922 ,  H01L2224/9221 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0209 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10454 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05 ,  H01L2224/29 ,  H01L2224/80 ,  H01L2924/00012

Abstract: A semiconductor assembly includes a substrate with electrically conductive regions and a semiconductor package. The semiconductor package includes a semiconductor die, first and second terminals, and a mold compound. The die has opposing first and second main surfaces, an edge disposed perpendicular to the first and second main surfaces, a first electrode at the first main surface, and a second electrode at the second main surface. The first terminal is attached to the first electrode. The second terminal is attached to the second electrode. The mold compound encloses at least part of the die and the first and second terminals so that each of the terminals has a side parallel with and facing away from the die that remains at least partly uncovered by the mold compound. The first and second terminals of the semiconductor package are connected to different ones of the electrically conductive regions of the substrate.

公开(公告)号：US09472483B2

公开(公告)日：2016-10-18

申请号：US14802341

申请日：2015-07-17

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sudeep Mandal ,  Sebastian T. Ventrone

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/48 ,  H01L23/373 ,  H01L21/768 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/367 ,  H01L21/4871 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/922 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2924/00012 ,  H01L2924/04941

Abstract: A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.

Abstract translation: 公开了一种由半导体材料制造的芯片，其可以包括位于从芯片背面的第一深度以下的有源器件，以及将热量从有源器件移除到芯片背面的结构。 该结构可以包括导热部分通孔（TCPV），其可以包括从芯片背侧朝向有源器件的深度的凹陷小于第一深度。 每个TCPV可以包括沉积在凹槽内并沉积在芯片背面的阻挡层。 每个TCPV还可以包括沉积在阻挡层上的导热层。 该结构还可以包括电连接到有源器件的穿硅通孔（TSV），其从芯片的背面延伸到有源器件侧，以将热量从有源器件导电移除到芯片的背面。

公开(公告)号：US20140353766A1

公开(公告)日：2014-12-04

申请号：US13905194

申请日：2013-05-30

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/34

CPC classification number: H01L25/065 ,  H01L23/051 ,  H01L23/34 ,  H01L23/36 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/04 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/08237 ,  H01L2224/08257 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/30181 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73151 ,  H01L2224/73251 ,  H01L2224/80898 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/922 ,  H01L2224/9221 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0209 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10454 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05 ,  H01L2224/29 ,  H01L2224/80 ,  H01L2924/00012

Abstract: A semiconductor assembly includes a substrate with electrically conductive regions and a semiconductor package. The semiconductor package includes a semiconductor die, first and second terminals, and a mold compound. The die has opposing first and second main surfaces, an edge disposed perpendicular to the first and second main surfaces, a first electrode at the first main surface, and a second electrode at the second main surface. The first terminal is attached to the first electrode. The second terminal is attached to the second electrode. The mold compound encloses at least part of the die and the first and second terminals so that each of the terminals has a side parallel with and facing away from the die that remains at least partly uncovered by the mold compound. The first and second terminals of the semiconductor package are connected to different ones of the electrically conductive regions of the substrate.

Abstract translation: 半导体组件包括具有导电区域的衬底和半导体封装。 半导体封装包括半导体管芯，第一和第二端子以及模具化合物。 模具具有相对的第一和第二主表面，垂直于第一和第二主表面设置的边缘，在第一主表面处的第一电极和在第二主表面处的第二电极。 第一端子附接到第一电极。 第二端子附接到第二电极。 模具化合物包围模具和第一和第二端子的至少一部分，使得每个端子具有与模具化合物保持至少部分未覆盖的模具平行并远离模具的一侧。 半导体封装的第一和第二端子连接到衬底的不同的导电区域。