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公开(公告)号：US20200152591A1
公开(公告)日：2020-05-14
申请号：US16742040
申请日：2020-01-14
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen
IPC: H01L23/00 , H01L25/065 , H01L23/525 , H01L23/498 , H01L23/367 , H01L23/14 , H01L21/56 , H01L25/00 , H01L21/683 , H01L23/48 , H01L21/768
Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
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公开(公告)号：US10461002B2
公开(公告)日：2019-10-29
申请号：US15646695
申请日：2017-07-11
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Chang-Lun Lu , Shih-Ching Chen
Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.
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公开(公告)号：US10141233B2
公开(公告)日：2018-11-27
申请号：US15008097
申请日：2016-01-27
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Chang-Lun Lu
Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.
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公开(公告)号：US20180261563A1
公开(公告)日：2018-09-13
申请号：US15975232
申请日：2018-05-09
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen
IPC: H01L23/00 , H01L25/00 , H01L21/56 , H01L23/525 , H01L23/498 , H01L23/48 , H01L23/367 , H01L23/14 , H01L21/768 , H01L21/683 , H01L25/065 , H01L23/31
CPC classification number: H01L24/13 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/525 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68359 , H01L2221/68381 , H01L2224/03912 , H01L2224/0401 , H01L2224/04105 , H01L2224/05552 , H01L2224/0557 , H01L2224/05571 , H01L2224/11003 , H01L2224/111 , H01L2224/11334 , H01L2224/1147 , H01L2224/1184 , H01L2224/11849 , H01L2224/12105 , H01L2224/13009 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/17181 , H01L2224/211 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/81191 , H01L2224/81193 , H01L2224/81444 , H01L2224/81801 , H01L2224/8185 , H01L2224/81903 , H01L2224/82101 , H01L2224/83 , H01L2224/83005 , H01L2224/831 , H01L2224/92 , H01L2224/9202 , H01L2224/922 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/00012 , H01L2924/00014 , H01L2924/15311 , H01L2924/16152 , H01L2924/18161 , H01L2924/3511 , H01L2924/3512 , H01L2224/11 , H01L2924/014 , H01L2224/81 , H01L2224/19 , H01L2924/00
Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
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5.发明申请SUBSTRATE STRUCTURE WITH FIRST AND SECOND CONDUCTIVE BUMPS HAVING DIFFERENT WIDTHS 有权具有不同宽度的第一和第二导电柱的基板结构公开(公告)号：US20160322323A1
公开(公告)日：2016-11-03
申请号：US14983738
申请日：2015-12-30
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chieh-Lung Lai , Lu-Yi Chen , Yu-Chuan Chen , Chang-Lun Lu
IPC: H01L23/00
CPC classification number: H01L24/14 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/05567 , H01L2224/13005 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2224/16227 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81815 , H01L2924/014 , H01L2924/206 , H01L2924/01047 , H01L2924/00014
Abstract: A substrate structure is provided, which includes a substrate body having a plurality of conductive pads, and a plurality of first conductive bumps and a plurality of second conductive bumps disposed on the conductive pads. Each of the second conductive bumps is less in width than each of the first conductive bumps, and is of a height with respect to the substrate body greater than a height of each of the first conductive bumps with respect to the substrate body. Therefore, the height difference between the first pre-solder layer and the second pre-solder layer after a reflow process can be compensated, and the first conductive bumps and the second conductive bumps thus have a uniform height.
Abstract translation: 提供了一种衬底结构，其包括具有多个导电焊盘的衬底本体，以及设置在导电焊盘上的多个第一导电凸块和多个第二导电凸块。 每个第二导电凸块的宽度小于每个第一导电凸块，并且相对于基板主体的高度大于每个第一导电凸块相对于基板主体的高度。 因此，可以补偿回流处理后的第一预焊锡层和第二预焊锡层之间的高度差，因此第一导电凸块和第二导电凸块具有均匀的高度。
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Patent Agency Ranking
公开(公告)号：US20130299961A1
公开(公告)日：2013-11-14
申请号：US13628549
申请日：2012-09-27
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Lu-Yi Chen
CPC classification number: H01L24/13 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/525 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68359 , H01L2221/68381 , H01L2224/03912 , H01L2224/0401 , H01L2224/04105 , H01L2224/0557 , H01L2224/05571 , H01L2224/11003 , H01L2224/111 , H01L2224/11334 , H01L2224/1147 , H01L2224/1184 , H01L2224/11849 , H01L2224/12105 , H01L2224/13009 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/17181 , H01L2224/211 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/81191 , H01L2224/81193 , H01L2224/81444 , H01L2224/81801 , H01L2224/8185 , H01L2224/81903 , H01L2224/82101 , H01L2224/83005 , H01L2224/831 , H01L2224/92 , H01L2224/9202 , H01L2224/922 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014 , H01L2924/15311 , H01L2924/16152 , H01L2924/18161 , H01L2924/3511 , H01L2924/3512 , H01L2224/11 , H01L2924/014 , H01L2224/81 , H01L2224/83 , H01L2224/19 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
Abstract translation: 半导体封装包括堆积结构; 以倒装芯片方式布置在积层结构上并具有穿过其的多个凸块的半导体; 设置在所述半导体芯片上的电子元件; 以及密封剂，其形成在积聚结构上并封装半导体芯片和电子元件，从而提高产品产量和整体散热效率。
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公开(公告)号：US10950507B2
公开(公告)日：2021-03-16
申请号：US15972837
申请日：2018-05-07
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Chi-Hsin Chiu , Shih-Kuang Chiu
IPC: G01R1/073 , H01L21/66 , H01L23/498 , H01L21/48
Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.
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公开(公告)号：US20190057911A1
公开(公告)日：2019-02-21
申请号：US16166811
申请日：2018-10-22
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Chang-Lun Lu
IPC: H01L21/66
CPC classification number: H01L22/14 , H01L21/561 , H01L21/568 , H01L23/3121 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15174 , H01L2924/15311 , H01L2924/19105 , H01L2924/19107 , H01L2924/00
Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.
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公开(公告)号：US20180254227A1
公开(公告)日：2018-09-06
申请号：US15972837
申请日：2018-05-07
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Chi-Hsin Chiu , Shih-Kuang Chiu
IPC: H01L21/66 , H01L23/498 , H01L21/48
CPC classification number: H01L22/14 , H01L21/486 , H01L22/20 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L2224/16
Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.
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公开(公告)号：US09997481B2
公开(公告)日：2018-06-12
申请号：US13628549
申请日：2012-09-27
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen
IPC: H01L23/498 , H01L23/31 , H01L25/065 , H01L21/56 , H01L23/00 , H01L23/14 , H01L23/367 , H01L23/525 , H01L21/768 , H01L23/48 , H01L21/683 , H01L25/00
CPC classification number: H01L24/13 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/525 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68359 , H01L2221/68381 , H01L2224/03912 , H01L2224/0401 , H01L2224/04105 , H01L2224/0557 , H01L2224/05571 , H01L2224/11003 , H01L2224/111 , H01L2224/11334 , H01L2224/1147 , H01L2224/1184 , H01L2224/11849 , H01L2224/12105 , H01L2224/13009 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/17181 , H01L2224/211 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/81191 , H01L2224/81193 , H01L2224/81444 , H01L2224/81801 , H01L2224/8185 , H01L2224/81903 , H01L2224/82101 , H01L2224/83005 , H01L2224/831 , H01L2224/92 , H01L2224/9202 , H01L2224/922 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014 , H01L2924/15311 , H01L2924/16152 , H01L2924/18161 , H01L2924/3511 , H01L2924/3512 , H01L2224/11 , H01L2924/014 , H01L2224/81 , H01L2224/83 , H01L2224/19 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
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