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    PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
    2.
    发明申请
    PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
    包装结构及其制造方法

    公开(公告)号：US20160079136A1

    公开(公告)日：2016-03-17

    申请号：US14823341

    申请日：2015-08-11

    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

    Inventor： Chi-Hsin Chiu ,  Shih-Kuang Chiu

    IPC: H01L23/31 ,  H01L21/52 ,  H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L21/768

    CPC classification number: H01L21/52 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2924/18162 ,  H01L2924/3511

    Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.

    Abstract translation: 提供一种包装结构，其包括：具有贯穿其中的空腔的框架; 接收在所述框架的空腔中的半导体芯片，其中所述半导体芯片具有从所述框架的空腔暴露的相对的有源和非活性表面; 在所述空腔中形成的电介质层，以接触和固定所述半导体芯片的位置，其中所述电介质层的表面与所述半导体芯片的有源表面所面对的所述框架的第一表面齐平; 以及形成在电介质层的表面上的电路结构，与框架的第一表面齐平并且电连接到半导体芯片的有源表面，从而节省制造成本并减小封装结构的厚度。

    Electrical testing method of interposer
    7.
    发明授权
    Electrical testing method of interposer 有权

    公开(公告)号：US10950507B2

    公开(公告)日：2021-03-16

    申请号：US15972837

    申请日：2018-05-07

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Lu-Yi Chen ,  Chi-Hsin Chiu ,  Shih-Kuang Chiu

    IPC: G01R1/073 ,  H01L21/66 ,  H01L23/498 ,  H01L21/48

    Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.

    Method for fabricating package structure
    8.
    发明申请
    Method for fabricating package structure 审中-公开

    公开(公告)号：US20190122898A1

    公开(公告)日：2019-04-25

    申请号：US16225230

    申请日：2018-12-19

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Chi-Hsin Chiu ,  Shih-Kuang Chiu

    IPC: H01L21/52 ,  H01L23/538 ,  H01L21/78 ,  H01L23/00

    Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.

    Package structure and fabrication method thereof
    9.
    发明授权
    Package structure and fabrication method thereof 有权

    公开(公告)号：US10199239B2

    公开(公告)日：2019-02-05

    申请号：US14823341

    申请日：2015-08-11

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Chi-Hsin Chiu ,  Shih-Kuang Chiu

    IPC: H01L21/52 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

    Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.

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