公开(公告)号：US20180068977A1

公开(公告)日：2018-03-08

申请号：US15558341

申请日：2015-10-23

Applicant: China Wafer Level CSP Co., Ltd.

Inventor： Zhiqi Wang ,  Ying Yang ,  Wei Wang

IPC: H01L23/00 ,  H01L23/488 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L21/568 ,  H01L23/488 ,  H01L24/01 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/24153 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15313 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A packaging method and a packaging structure are provided. The method includes: providing a first substrate and a second substrate, the second substrate having a first surface and a second surface opposite to each other, a side surface of the first substrate being adhered to the first surface of the second substrate via an adhesive layer; forming a groove structure on the second surface of the second substrate; providing a base, the base having a first surface and a second surface opposite to each other, the first surface of the base including a sensing region and multiple bonding pads around the sensing region; and laminating the second surface of the second substrate with the first surface of the base to form a cavity between the groove structure and the base, such that the sensing region is located in the cavity.

公开(公告)号：US20140021629A1

公开(公告)日：2014-01-23

申请号：US13654754

申请日：2012-10-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。

公开(公告)号：US11676948B2

公开(公告)日：2023-06-13

申请号：US17337752

申请日：2021-06-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kong-Toon Ng ,  Hung-Ho Lee ,  Chee-Key Chung ,  Chang-Fu Lin ,  Chi-Hsin Chiu

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L24/16 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/24153 ,  H01L2224/73209 ,  H01L2224/82005 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.

公开(公告)号：US09812340B2

公开(公告)日：2017-11-07

申请号：US15074110

申请日：2016-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

公开(公告)号：US09324585B2

公开(公告)日：2016-04-26

申请号：US13654754

申请日：2012-10-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。

公开(公告)号：US20230268328A1

公开(公告)日：2023-08-24

申请号：US18309756

申请日：2023-04-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Kong-Toon Ng ,  Hung-Ho Lee ,  Chee-Key Chung ,  Chang-Fu LIN ,  Chi-Hsin Chiu

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L24/82 ,  H01L24/81 ,  H01L24/24 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/73209 ,  H01L2224/82005 ,  H01L2224/16145 ,  H01L2224/24153 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.

公开(公告)号：US20160196990A1

公开(公告)日：2016-07-07

申请号：US15074110

申请日：2016-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。

公开(公告)号：US20150102829A1

公开(公告)日：2015-04-16

申请号：US14401116

申请日：2013-05-14

Applicant: CRUCIALTEC CO., LTD.

Inventor： Dong Nam Son ,  Young Moon Park ,  Ki Don Kim

IPC: G06K9/00 ,  H01L21/56

CPC classification number: G06K9/0002 ,  G06K9/00053 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/24153 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: The objective of the present invention is to provide a fingerprint sensor package having a novel structure and a method for manufacturing same, the fingerprint sensor package enabled with obtaining an accurate fingerprint image by minimizing the distance between a top surface of a sensing portion in a fingerprint sensor and a fingerprint, so as to improve mechanical strength and tolerance to electrostatic discharge compared to existing fingerprint sensor packages. To this end, the present invention provides the fingerprint sensor package and the method for manufacturing same, the fingerprint sensor package comprising: the fingerprint sensor comprising a sensing portion on which pixels for detecting fingerprint data are arranged in an array; via frame being arranged around and spaced apart from the fingerprint sensor and comprising via; a connection electrode for electrically connecting a bonding pad, which is provided on an upper surface of the fingerprint sensor for external access, and the via hole on the via frames; a conductive pattern compring a driving electrode for generating a driving signal for the fingerprint sensor; a mold body which is formed so that the fingerprint sensor and the via frame are integrated; and a protective layer for covering the upper surface of the fingerprint sensor.

Abstract translation: 本发明的目的是提供一种具有新颖结构的指纹传感器封装及其制造方法，该指纹传感器封装使得能够通过最小化指纹中的感测部分的顶表面之间的距离获得准确的指纹图像 传感器和指纹，以便与现有的指纹传感器封装相比，提高机械强度和对静电放电的耐受性。 为此，本发明提供了一种指纹传感器封装及其制造方法，所述指纹传感器封装包括：所述指纹传感器包括感测部分，用于检测指纹数据的像素排列在其上; 通过框架布置在指纹传感器周围并与指纹传感器间隔开并且包括通孔; 连接电极，用于电连接设置在用于外部通路的指纹传感器的上表面上的接合焊盘和通孔上的通孔; 导电图案，其包括用于产生用于指纹传感器的驱动信号的驱动电极; 形成为使得指纹传感器和通孔框架一体化的模具体; 以及用于覆盖指纹传感器的上表面的保护层。