公开(公告)号：US12119320B2

公开(公告)日：2024-10-15

申请号：US17869118

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Li-Hsien Huang ,  An-Jhih Su ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/54 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/16 ,  H01L21/486 ,  H01L21/54 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49827 ,  H01L24/01 ,  H01L24/11 ,  H01L24/18 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/11849 ,  H01L2224/16013 ,  H01L2224/16104 ,  H01L2224/16221 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.

公开(公告)号：US11842972B2

公开(公告)日：2023-12-12

申请号：US17752835

申请日：2022-05-24

Applicant: ROHM CO., LTD.

Inventor： Kazumasa Tanida ,  Osamu Miyata

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/52 ,  H10K50/842

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/562 ,  H01L24/17 ,  H01L24/28 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/01 ,  H01L24/75 ,  H01L2224/01 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/153 ,  H01L2924/183 ,  H01L2924/3512 ,  H10K50/8426

Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

公开(公告)号：US11810877B2

公开(公告)日：2023-11-07

申请号：US17454937

申请日：2021-11-15

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar K. Patel ,  Mark A. Webster ,  Craig S. Appel

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/522 ,  H01L21/20 ,  G02B6/122 ,  G02B6/12 ,  G02B6/30

CPC classification number: H01L24/01 ,  H01L21/2007 ,  H01L23/5222 ,  G02B6/1225 ,  G02B6/305 ,  G02B2006/12061

Abstract: Embodiments herein describe providing a decoupling capacitor on a first wafer (or substrate) that is then bonded to a second wafer to form an integrated decoupling capacitor. Using wafer bonding means that the decoupling capacitor can be added to the second wafer without having to take up space in the second wafer. In one embodiment, after bonding the first and second wafers, one or more vias are formed through the second wafer to establish an electrical connection between the decoupling capacitor and bond pads on a first surface of the second wafer. An electrical IC can then be flip chipped bonded to the first surface. As part of coupling the decoupling capacitor to the electrical IC, the decoupling capacitor is connected between the rails of a power source (e.g., VDD and VSS) that provides power to the electrical IC.

公开(公告)号：US11807528B2

公开(公告)日：2023-11-07

申请号：US16718730

申请日：2019-12-18

Applicant: NICHIA CORPORATION

Inventor： Shimpei Kinoshita ,  Shoji Hosokawa

IPC: C01B21/072 ,  H01L23/00

CPC classification number: C01B21/072 ,  H01L24/01 ,  C01P2002/74 ,  C01P2004/64

Abstract: Provided are silicon-containing aluminum nitride particles having a high reflectance, a method for producing the same, and a light emitting device. In certain embodiment, silicon-containing aluminum nitride particles having a total amount of aluminum and nitrogen of 90% by mass or more, a content of silicon in a range of 1.5% by mass or more and 4.0% by mass or less, and a content of oxygen in a range of 0.5% by mass or more and 2.0% by mass or less, and having an average reflectance in a wavelength range of 380 nm or more and 730 nm or less of 85% or more.

公开(公告)号：US11724933B2

公开(公告)日：2023-08-15

申请号：US16655127

申请日：2019-10-16

Applicant: ROHM Co., Ltd.

Inventor： Martin Heller ,  Toma Fujita

IPC: B81C1/00 ,  B32B15/04 ,  B32B15/20 ,  H01L23/02 ,  B81B7/00 ,  H01L23/00

CPC classification number: B81C1/00269 ,  B32B15/043 ,  B32B15/20 ,  B81B7/0032 ,  B81C1/00261 ,  H01L23/02 ,  H01L24/01 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L24/94 ,  B81B2203/0315 ,  B81C2203/019 ,  B81C2203/0127 ,  B81C2203/035

Abstract: A MEMS device formed in a first semiconductor substrate is sealed using a second semiconductor substrate. To achieve this, an Aluminum Germanium structure is formed above the first substrate, and a polysilicon layer is formed above the second substrate. The first substrate is covered with the second substrate so as to cause the polysilicon layer to contact the Aluminum Germanium structure. Thereafter, eutectic bonding is performed between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form an AlGeSi sealant thereby to seal the MEMS device. Optionally, the Germanium Aluminum structure includes, in part, a layer of Germanium overlaying a layer of Aluminum.

公开(公告)号：US20180174987A1

公开(公告)日：2018-06-21

申请号：US15794000

申请日：2017-10-26

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Mikiya CHOUNABAYASHI ,  Ryohei MAKINO ,  Hayato NAKANO

IPC: H01L23/64 ,  H01L23/482 ,  H01L23/00

CPC classification number: H01L23/647 ,  H01L23/4827 ,  H01L24/01 ,  H01L24/14 ,  H01L25/072 ,  H01L25/162 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107

Abstract: A semiconductor device is provided that includes a semiconductor chip having a main terminal and a control terminal, a main connection pin electrically connected to the main terminal, and a control connection pin electrically connected to the control terminal and having an electrical resistance higher than that of the main connection pin. The control connection pin may be a control internal connection pin or a control external connection pin. The control connection pin may include material having an electrical resistivity higher than that of material of the main connection pin. The control connection pin may have a shape different from that of the main connection pin.

公开(公告)号：US10002812B2

公开(公告)日：2018-06-19

申请号：US15422274

申请日：2017-02-01

Applicant: Semikron Elektronik GmbH & Co., KG

Inventor： Christian Göbl ,  Clemens Vennebusch

IPC: H01L23/28 ,  H01L23/10 ,  H01L23/049 ,  H01L23/40 ,  H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L23/053

CPC classification number: H01L23/10 ,  H01L23/049 ,  H01L23/053 ,  H01L23/3735 ,  H01L23/4006 ,  H01L23/4951 ,  H01L23/49517 ,  H01L23/49531 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49811 ,  H01L24/01 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2023/4025 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/00014 ,  H05K7/209 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/32225 ,  H01L2924/00012

Abstract: A power semiconductor module having a pressure application body, a circuit carrier, which is embodied with a first conductor track, a power semiconductor element arranged thereon and an internal connecting device, and also having a housing which is embodied with a guide device arranged therein, with a connecting element. The connecting element is embodied as a bolt with first and second end sections and an intermediate section therebetween, wherein the first end section rests on the circuit carrier and is electrically conductively connected thereto; the second end section projects out of the housing through a cutout; and wherein the connecting element is arranged in the assigned guide device. The pressure application body has a first rigid partial body and a second elastic partial body, wherein the second partial body protrudes out of the first partial body in the direction of the housing.

公开(公告)号：US09953870B2

公开(公告)日：2018-04-24

申请号：US15488514

申请日：2017-04-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L21/77 ,  H01L29/66 ,  H01L27/10 ,  H01L23/40 ,  H01L23/00 ,  H01L23/31 ,  H01L27/02 ,  B82Y10/00 ,  H01L21/84 ,  H01L23/528 ,  H01L21/683 ,  H01L21/762 ,  H01L27/06 ,  H01L29/78 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/10 ,  G11C16/04 ,  H01L23/36 ,  H01L23/367 ,  H01L27/088

CPC classification number: H01L21/77 ,  B82Y10/00 ,  G11C16/0408 ,  G11C16/0483 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4012 ,  H01L23/5286 ,  H01L24/01 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/249 ,  H01L28/00 ,  H01L29/1033 ,  H01L29/66257 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

公开(公告)号：US20170263535A1

公开(公告)日：2017-09-14

申请号：US15417245

申请日：2017-01-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hayato NAKANO ,  Hideyo NAKAMURA

IPC: H01L23/48 ,  H05K1/02 ,  H02M7/00

CPC classification number: H01L23/48 ,  H01L24/01 ,  H02M7/003 ,  H05K1/0213

Abstract: A semiconductor device including a semiconductor module 10A, a semiconductor module 10B that has a lower switching voltage threshold than the semiconductor module 10A, and busbars 331 and 32 that connect the semiconductor module 10A and the semiconductor module 10B in parallel to a common terminal. The semiconductor module 10B is connected at a connection point on the busbar 32 at which the inductance relative to the common terminal is higher than that of the semiconductor module 10A. The semiconductor module 10B with the low threshold voltage is turned ON faster than the semiconductor module 10A with the high threshold voltage for input of a common switching voltage, but can restrict the rising of the current due to the high inductance of the busbar 32, thereby enabling restriction of the current imbalance.

公开(公告)号：US09721865B2

公开(公告)日：2017-08-01

申请号：US14824706

申请日：2015-08-12

Applicant: ROHM CO., LTD.

Inventor： Kazumasa Tanida ,  Osamu Miyata

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L51/52 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/562 ,  H01L24/01 ,  H01L24/17 ,  H01L24/28 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L51/5246 ,  H01L2224/01 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/153 ,  H01L2924/183 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.