公开(公告)号：US20240250058A1

公开(公告)日：2024-07-25

申请号：US18416079

申请日：2024-01-18

申请人： STMicroelectronics International N.V.

发明人： Mauro MAZZOLA ,  Fabio MARCHISI

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/40 ,  H01L23/49838 ,  H01L24/35 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/355 ,  H01L2224/40155 ,  H01L2224/48155 ,  H01L2224/73221 ,  H01L2924/153

摘要： A semiconductor die is arranged at a die mounting location of a substrate. The substrate includes an array of electrically conductive leads at the periphery of the substrate. Electrical coupling is provided between the semiconductor die and selected ones of the electrically conductive leads in the array of electrically conductive leads via electrically conductive ribbons. Each ribbon has a body portion with a first width as well as first and second end portions bonded to the semiconductor die and to the electrically conductive leads, respectively. At least one of the first and second end portions of the electrically conductive ribbon includes a tapered portion having a second width smaller than the first width of the body portion.

公开(公告)号：US09818734B2

公开(公告)日：2017-11-14

申请号：US14624136

申请日：2015-02-17

申请人： STATS ChipPAC, Ltd.

发明人： Yaojian Lin ,  Kang Chen

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/552 ,  H01L21/66 ,  H01L23/538

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/568 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/82

摘要： A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices.

公开(公告)号：US09818635B2

公开(公告)日：2017-11-14

申请号：US14982142

申请日：2015-12-29

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Lu-Yi Chen ,  Chang-Lun Lu

IPC分类号： H01L29/40 ,  H01L21/683 ,  H01L23/498 ,  H01L23/373 ,  H01L21/66 ,  H01L21/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/16

CPC分类号： H01L21/6835 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/568 ,  H01L22/14 ,  H01L23/147 ,  H01L23/373 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2224/45099

摘要： An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.

公开(公告)号：US20170092630A1

公开(公告)日：2017-03-30

申请号：US15272568

申请日：2016-09-22

申请人： AT&S Austria Technologie & Systemtechnik Aktiengesellschaft

发明人： Gerald Weis ,  Christian Vockenberger ,  Roland Sekavcnik

IPC分类号： H01L25/16 ,  H05K1/02 ,  H05K1/11 ,  H05K7/20 ,  H01L23/467 ,  H01L25/07 ,  H01L23/00 ,  H05K1/18 ,  H01L23/538

CPC分类号： H01L25/16 ,  H01L23/3677 ,  H01L23/467 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/074 ,  H01L25/105 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2225/1035 ,  H01L2225/1047 ,  H01L2225/1094 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/1426 ,  H01L2924/1436 ,  H01L2924/153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/0212 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K1/185 ,  H05K7/20154 ,  H05K2201/10015 ,  H05K2201/10166 ,  Y02P70/611

摘要： In a connection system for electronic components (1) comprising a plurality of insulating layers (2) and conductive layers (3) and further comprising at least one embedded electronic component (4) embedded within at least one of the plurality of insulating layers (2) and conductive layers (3) the at least one embedded electronic component (4) is at least one first transistor having a bulk terminal thereof in thermal contact with a thermal duct (6) comprised of a plurality of vias (7) reaching through at least one of an insulating layer (2) and a conductive layer (3) of the connection system for electronic components (1) and emerging on a first outer surface (8) of the connection system for electronic components (1) under a first surface-mounted component (10).

公开(公告)号：US20150179616A1

公开(公告)日：2015-06-25

申请号：US14624136

申请日：2015-02-17

申请人： STATS ChipPAC, Ltd.

发明人： Yaojian Lin ,  Kang Chen

IPC分类号： H01L25/065 ,  H01L25/00

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/568 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/82

摘要： A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices.

摘要翻译： 半导体器件具有形成在衬底上的第一构建互连结构。 第一构建互连结构包括绝缘层和形成在绝缘层上的导电层。 垂直互连结构和半导体管芯设置在第一堆积互连结构之上。 半导体管芯，第一堆叠互连结构和衬底设置在载体上。 密封剂沉积在半导体管芯，第一堆积互连结构和衬底上。 第二堆积互连结构形成在密封剂上。 第二堆叠互连结构通过垂直互连结构电连接到第一堆叠互连结构。 衬底提供结构支撑并防止形成第一和第二堆积互连结构期间的翘曲。 在形成第二堆积互连结构之后去除衬底。 绝缘层的一部分被去除，暴露出导电层用于随后堆叠的半导体器件的电互连。

公开(公告)号：US20180006008A1

公开(公告)日：2018-01-04

申请号：US15705646

申请日：2017-09-15

申请人： STATS ChipPAC Pte. Ltd.

发明人： Yaojian Lin ,  Kang Chen

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L23/552 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L21/56 ,  H01L21/66

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/568 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/82

摘要： A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices.

公开(公告)号：US20170301640A1

公开(公告)日：2017-10-19

申请号：US15635478

申请日：2017-06-28

申请人： ROHM CO., LTD.

发明人： Kazumasa TANIDA ,  Osamu MIYATA

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/16 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/562 ,  H01L24/01 ,  H01L24/17 ,  H01L24/28 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L51/5246 ,  H01L2224/01 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/153 ,  H01L2924/183 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

公开(公告)号：US09691707B2

公开(公告)日：2017-06-27

申请号：US15130452

申请日：2016-04-15

申请人： STATS ChipPAC, Ltd.

发明人： HeeJo Chi ,  HanGil Shin ,  NamJu Cho

IPC分类号： H01L23/48 ,  H01L23/02 ,  H01L21/00 ,  H01L23/538 ,  H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L24/19 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/25171 ,  H01L2224/82039 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/153 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2224/08

摘要： A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.

公开(公告)号：US20170110407A1

公开(公告)日：2017-04-20

申请号：US14885757

申请日：2015-10-16

申请人： Xilinx, Inc.

发明人： Raghunandan Chaware ,  Amitava Majumdar ,  Glenn O'Rourke ,  Inderjit Singh

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L23/5385 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/152 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/78 ,  H01L2221/68304 ,  H01L2224/81 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/11 ,  H01L2221/68381 ,  H01L22/00 ,  H01L2224/1181

摘要： Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

公开(公告)号：US09117774B2

公开(公告)日：2015-08-25

申请号：US14276255

申请日：2014-05-13

申请人： ROHM CO., LTD.

发明人： Kazumasa Tanida ,  Osamu Miyata

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/31 ,  H01L21/56 ,  H01L51/52 ,  H01L23/00

CPC分类号： H01L24/16 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/562 ,  H01L24/01 ,  H01L24/17 ,  H01L24/28 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L51/5246 ,  H01L2224/01 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/153 ,  H01L2924/183 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.

摘要翻译： 半导体器件（1,21）包括固态器件（2,22），半导体芯片（3），其具有形成有功能元件（4）的功能表面（3a），并且结合在表面 的固态器件，其功能表面面向固态器件的表面，并且在其功能表面和固态器件的表面之间保持预定距离的同时，设置在表面上的绝缘膜（6） （2a，22a），并且当面向半导体芯片的固态器件的表面在平面中垂直向下观察时，具有比半导体芯片尺寸更大的开口（6a），并且 密封层（7），其密封固态器件和半导体芯片之间的空间。