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1.
公开(公告)号:US11742316B2
公开(公告)日:2023-08-29
申请号:US17897086
申请日:2022-08-26
发明人: Yu Zhang , Chengqiang Cui , Peilin Liang , Jin Tong , Guannan Yang
IPC分类号: H01L23/00
CPC分类号: H01L24/81 , H01L24/11 , H01L24/16 , H01L2224/11015 , H01L2224/1181 , H01L2224/16227 , H01L2224/81007 , H01L2224/81055 , H01L2224/8184 , H01L2224/81203 , H01L2224/81207 , H01L2224/81224 , H01L2224/81911 , H01L2924/381 , H01L2924/3841
摘要: This application relates to semiconductor manufacturing, and more particularly to an interconnect structure for semiconductors with an ultra-fine pitch and a forming method thereof. The forming method includes: preparing copper nanoparticles using a vapor deposition device, where coupling parameters of the vapor deposition device are adjusted to control an initial particle size of the copper nanoparticles; depositing the copper nanoparticles on a substrate; invertedly placing a chip with copper pillars as I/O ports on the substrate; and subjecting the chip and the substrate to hot-pressing sintering to enable the bonding.
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2.
公开(公告)号:US20190244918A1
公开(公告)日:2019-08-08
申请号:US16390628
申请日:2019-04-22
发明人: Chia-Lun Chang , Chung-Shi Liu , Hsiu-Jen Lin , Hsien-Wei Chen , Ming-Da Cheng , Wei-Yu Chen
IPC分类号: H01L23/00 , H01L23/498 , H01L21/56 , H01L23/538 , H01L21/683 , H01L23/29
CPC分类号: H01L24/05 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/293 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2221/68359 , H01L2224/02126 , H01L2224/02166 , H01L2224/02175 , H01L2224/03015 , H01L2224/0346 , H01L2224/03828 , H01L2224/0383 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05017 , H01L2224/05025 , H01L2224/05147 , H01L2224/05557 , H01L2224/05559 , H01L2224/05567 , H01L2224/05647 , H01L2224/10156 , H01L2224/11005 , H01L2224/1132 , H01L2224/11334 , H01L2224/11416 , H01L2224/11424 , H01L2224/1181 , H01L2224/11849 , H01L2224/119 , H01L2224/12105 , H01L2224/13026 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/215 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00 , H01L2924/00014 , H01L2924/01029 , H01L2924/0105 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/06 , H01L2924/0665 , H01L2924/15311 , H01L2924/18162 , H01L2924/00012 , H01L2924/01051 , H01L2924/01047 , H01L2924/01022 , H01L2924/01028 , H01L2924/01046 , H01L2924/01079
摘要: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
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公开(公告)号:US20190013293A1
公开(公告)日:2019-01-10
申请号:US16037537
申请日:2018-07-17
申请人: TDK CORPORATION
发明人: Makoto ORIKASA , Hideyuki SEIKE , Yuhei HORIKAWA , Hisayuki ABE
IPC分类号: H01L23/00 , H01L25/065 , H01L25/00
CPC分类号: H01L24/81 , H01L24/11 , H01L24/13 , H01L24/95 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05655 , H01L2224/11005 , H01L2224/11334 , H01L2224/1146 , H01L2224/1181 , H01L2224/1184 , H01L2224/11849 , H01L2224/13017 , H01L2224/13022 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16148 , H01L2224/81002 , H01L2224/81014 , H01L2224/81022 , H01L2224/81035 , H01L2224/81047 , H01L2224/81048 , H01L2224/81065 , H01L2224/81143 , H01L2224/81815 , H01L2224/95146 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01015 , H01L2924/00012 , H01L2924/01047 , H01L2924/014 , H01L2924/01029 , H01L2924/01083
摘要: A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.
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公开(公告)号:US10072237B2
公开(公告)日:2018-09-11
申请号:US15227450
申请日:2016-08-03
发明人: Randy Li-Kai Chang , Gene Everad Parris , Hsiu Mei Chen , Yi-Chia Lee , Wen Dar Liu , Tianniu Chen , Laura M. Matz , Ryback Li Chang Lo , Ling-Jen Meng
IPC分类号: C11D11/00 , H01L23/00 , C11D7/26 , C11D7/34 , C11D7/50 , C11D7/32 , C11D3/00 , G03F7/42 , H01L21/311
CPC分类号: C11D11/0047 , C11D3/0073 , C11D7/265 , C11D7/3209 , C11D7/34 , C11D7/5009 , C11D7/5013 , C11D7/5022 , G03F7/425 , G03F7/426 , H01L21/31133 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2224/02311 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0401 , H01L2224/05073 , H01L2224/05082 , H01L2224/05147 , H01L2224/05155 , H01L2224/05171 , H01L2224/05614 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05672 , H01L2224/11462 , H01L2224/1147 , H01L2224/1148 , H01L2224/1181 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/81191 , H01L2224/94 , H01L2924/00012 , H01L2924/00014 , H01L2924/01029 , H01L2924/01028 , H01L2924/014 , H01L2224/11 , H01L2924/01047
摘要: It is disclosed a photoresist cleaning composition for stripping a photoresist pattern having a film thickness of 3-150 μm, which contains (a) quaternary ammonium hydroxide (b) a mixture of water-soluble organic solvents (c) at least one corrosion inhibitor and (d) water, and a method for treating a substrate therewith.
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公开(公告)号:US20180254255A1
公开(公告)日:2018-09-06
申请号:US15449361
申请日:2017-03-03
申请人: TDK CORPORATION
发明人: Makoto ORIKASA , Hideyuki SEIKE , Yuhei HORIKAWA , Hisayuki ABE
IPC分类号: H01L23/00 , H01L25/00 , H01L25/065
CPC分类号: H01L24/81 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2224/05655 , H01L2224/11005 , H01L2224/11334 , H01L2224/1146 , H01L2224/1181 , H01L2224/1184 , H01L2224/11849 , H01L2224/13017 , H01L2224/13022 , H01L2224/13083 , H01L2224/16148 , H01L2224/81014 , H01L2224/81035 , H01L2224/81047 , H01L2224/81048 , H01L2224/81065 , H01L2224/81143 , H01L2224/81815 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01015 , H01L2924/00012
摘要: A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.
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公开(公告)号:US09978656B2
公开(公告)日:2018-05-22
申请号:US13406270
申请日:2012-02-27
申请人: Tsung-Shu Lin , Han-Ping Pu , Ming-Da Cheng , Chang-Chia Huang , Hao-Juin Liu
发明人: Tsung-Shu Lin , Han-Ping Pu , Ming-Da Cheng , Chang-Chia Huang , Hao-Juin Liu
CPC分类号: H01L23/293 , H01L21/568 , H01L23/3157 , H01L24/02 , H01L24/03 , H01L24/04 , H01L24/05 , H01L24/06 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/14 , H01L2224/0346 , H01L2224/0347 , H01L2224/0401 , H01L2224/05541 , H01L2224/05572 , H01L2224/05647 , H01L2224/10126 , H01L2224/1146 , H01L2224/1147 , H01L2224/1181 , H01L2224/1191 , H01L2224/13005 , H01L2224/13007 , H01L2224/13022 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13155 , H01L2224/13164 , H01L2224/16237 , H01L2224/73104 , H01L2224/81193 , H01L2224/81411 , H01L2224/81413 , H01L2224/81416 , H01L2224/81439 , H01L2224/81447 , H01L2224/81455 , H01L2924/00014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00012 , H01L2924/206 , H01L2924/207 , H01L2924/01082 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要: The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.
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公开(公告)号:US09972590B2
公开(公告)日:2018-05-15
申请号:US15202195
申请日:2016-07-05
发明人: Deog Soon Choi , Ah Ron Lee , Hyun-Mo Ku
IPC分类号: H01L23/52 , H01L23/00 , H01L23/498
CPC分类号: H01L24/09 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/81 , H01L2224/03828 , H01L2224/05554 , H01L2224/05555 , H01L2224/0912 , H01L2224/0951 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/1147 , H01L2224/1181 , H01L2224/1183 , H01L2224/11849 , H01L2224/119 , H01L2224/13007 , H01L2224/13014 , H01L2224/13016 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/1411 , H01L2224/1712 , H01L2224/175 , H01L2224/81192 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81815 , H05K3/34 , H01L2924/014 , H01L2924/0665 , H01L2924/00014 , H01L2924/00012
摘要: A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of pads disposed on the first face of the substrate, each of the plurality of pads including a first face and an opposing second face that is in contact with the first face of the substrate. The semiconductor package is further described to include a plurality of solder-on-pad structures provided on a first of the plurality of pads.
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公开(公告)号:US20180132398A1
公开(公告)日:2018-05-10
申请号:US15670121
申请日:2017-08-07
发明人: Eric Frank Schulte
CPC分类号: H05K13/046 , B32B38/0008 , B32B2310/14 , B32B2457/00 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0381 , H01L2224/0401 , H01L2224/05552 , H01L2224/05557 , H01L2224/05568 , H01L2224/05655 , H01L2224/11334 , H01L2224/1181 , H01L2224/11831 , H01L2224/13099 , H01L2224/131 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/16145 , H01L2224/81011 , H01L2224/81013 , H01L2224/81054 , H01L2224/81099 , H01L2224/81191 , H01L2224/81193 , H01L2224/812 , H01L2224/81201 , H01L2224/81365 , H01L2224/81895 , H01L2224/81897 , H01L2225/06513 , H01L2225/06565 , H01L2924/00 , H01L2924/0001 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/1431 , H01L2924/1461
摘要: Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.
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公开(公告)号:US20180132397A1
公开(公告)日:2018-05-10
申请号:US15670116
申请日:2017-08-07
发明人: Eric Frank Schulte
CPC分类号: H05K13/046 , B32B38/0008 , B32B2310/14 , B32B2457/00 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0381 , H01L2224/0401 , H01L2224/05552 , H01L2224/05557 , H01L2224/05568 , H01L2224/05655 , H01L2224/11334 , H01L2224/1181 , H01L2224/11831 , H01L2224/13099 , H01L2224/131 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/16145 , H01L2224/81011 , H01L2224/81013 , H01L2224/81054 , H01L2224/81099 , H01L2224/81191 , H01L2224/81193 , H01L2224/812 , H01L2224/81201 , H01L2224/81365 , H01L2224/81895 , H01L2224/81897 , H01L2225/06513 , H01L2225/06565 , H01L2924/00 , H01L2924/0001 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/1431 , H01L2924/1461
摘要: Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.
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公开(公告)号:US20180132396A1
公开(公告)日:2018-05-10
申请号:US15670112
申请日:2017-08-07
发明人: Eric Frank Schulte
CPC分类号: H05K13/046 , B32B38/0008 , B32B2310/14 , B32B2457/00 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0381 , H01L2224/0401 , H01L2224/05552 , H01L2224/05557 , H01L2224/05568 , H01L2224/05655 , H01L2224/11334 , H01L2224/1181 , H01L2224/11831 , H01L2224/13099 , H01L2224/131 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/16145 , H01L2224/81011 , H01L2224/81013 , H01L2224/81054 , H01L2224/81099 , H01L2224/81191 , H01L2224/81193 , H01L2224/812 , H01L2224/81201 , H01L2224/81365 , H01L2224/81895 , H01L2224/81897 , H01L2225/06513 , H01L2225/06565 , H01L2924/00 , H01L2924/0001 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/1431 , H01L2924/1461
摘要: Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.
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