公开(公告)号：US11869840B2

公开(公告)日：2024-01-09

申请号：US17752224

申请日：2022-05-24

申请人： Infineon Technologies AG

发明人： Ralf Siemieniec ,  Dethard Peters ,  Roland Rupp

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L29/45 ,  H01L29/16

CPC分类号： H01L23/53238 ,  H01L21/7685 ,  H01L24/45 ,  H01L29/1608 ,  H01L29/45 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/05181 ,  H01L2224/05672 ,  H01L2224/05679 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147

摘要： A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

公开(公告)号：US20170033075A1

公开(公告)日：2017-02-02

申请号：US15294508

申请日：2016-10-14

申请人： Advanced Semiconductor, Inc.

发明人： Min-Fong SHU ,  Yi-Hsiu TSENG ,  Kuan-Neng CHEN ,  Shu-Chiao KUO

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/1182 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13623 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13663 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13676 ,  H01L2224/13678 ,  H01L2224/13687 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81096 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/81463 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81898 ,  H01L2224/83104 ,  H01L2224/83193 ,  H01L2224/92125 ,  H01L2924/00015 ,  H01L2924/15311 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2224/8109 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053

摘要： A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.

摘要翻译： 一种接合结构的制造方法包括：（a）提供基板，其中所述基板包括顶表面和邻近所述基板顶表面设置的至少一个接合焊盘，至少一个接合焊盘，其具有倾斜表面，其具有第一 坡; （b）提供半导体元件，其中所述半导体元件包括至少一个支柱，并且至少一个支柱具有具有第二斜率的侧壁，其中所述第一斜率的绝对值小于所述第二斜率的绝对值; 和（c）将至少一个柱结合到所述至少一个接合焊盘中相应的一个焊盘的倾斜表面的一部分上。

公开(公告)号：US09397055B2

公开(公告)日：2016-07-19

申请号：US14290448

申请日：2014-05-29

申请人： Infineon Technologies AG

发明人： Paul Ganitzer ,  Rudolf Zelsacher

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/82

CPC分类号： H01L24/03 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/82 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0312 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05672 ,  H01L2224/80203 ,  H01L2224/80825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05624

摘要： In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing.

摘要翻译： 在本发明的实施例中，形成半导体器件的方法包括提供包括第一芯片区域和第二芯片区域的半导体衬底。 在第一芯片区域上形成第一接触焊盘，并且在第二芯片区域上形成第二接触焊盘。 第一和第二接触焊盘至少与半导体衬底一样厚。 该方法还包括在第一和第二接触焊盘之间切割通过半导体衬底。 从包括第一接触焊盘和第二接触焊盘的半导体衬底的一侧进行切割。 导电衬垫形成在半导体衬底的第一接触焊盘和第二接触焊盘和通过切割而暴露的侧壁之间。

公开(公告)号：US20160126216A1

公开(公告)日：2016-05-05

申请号：US14931021

申请日：2015-11-03

申请人： Infineon Technologies AG

发明人： Alexander HEINRICH ,  Hermann GRUBER

IPC分类号： H01L23/00 ,  H01L21/683

CPC分类号： H01L24/83 ,  B23K20/023 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/75 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2224/04026 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/27462 ,  H01L2224/29019 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29164 ,  H01L2224/29169 ,  H01L2224/30181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/33181 ,  H01L2224/75252 ,  H01L2224/7598 ,  H01L2224/83005 ,  H01L2224/83193 ,  H01L2224/83204 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83898 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3656 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/8384 ,  H01L2224/27505 ,  H01L2224/83815

摘要： Various embodiments provide a method of forming an interconnection between an electric component and an electronic component, wherein the method comprises forming a first interconnection sublayer on an electric component, wherein the first interconnection sublayer comprises a metal and has a main surface opposite to the electric component, wherein the main surface has a first surface roughness; forming a second interconnection sublayer on an electronic component, wherein the second interconnection sublayer comprises the metal and has a surface opposite to the electronic component, wherein the surface has a second surface roughness, wherein the first surface roughness and the second surface roughness are in the same order of magnitude; and interconnecting the first interconnection sublayer and the second interconnection sublayer by contacting the same and applying pressure and heat to the contacted first and second interconnection sublayers.

摘要翻译： 各种实施例提供了一种在电气部件和电子部件之间形成互连的方法，其中所述方法包括在电气部件上形成第一互连子层，其中所述第一互连子层包括金属并且具有与所述电气部件相对的主表面 ，其中所述主表面具有第一表面粗糙度; 在电子部件上形成第二互连子层，其中所述第二互连子层包括所述金属并具有与所述电子部件相对的表面，其中所述表面具有第二表面粗糙度，其中所述第一表面粗糙度和所述第二表面粗糙度在 相同数量级; 并且通过使所述第一互连子层和所述第二互连子层接触所述第一互连子层和所述第二互连子层，并且将所述第一互连子层和所述第二互连子层与所接触的第一和第二互连子层施加压力和热量。

公开(公告)号：US09059003B2

公开(公告)日：2015-06-16

申请号：US14364555

申请日：2013-02-22

申请人： NIPPON MICROMETAL CORPORATION ,  WASEDA UNIVERSITY

发明人： Kohei Tatsumi ,  Takashi Yamada ,  Daizo Oda

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/03444 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/32245 ,  H01L2224/43 ,  H01L2224/4312 ,  H01L2224/43125 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45005 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45611 ,  H01L2224/45618 ,  H01L2224/45624 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45647 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/45666 ,  H01L2224/45669 ,  H01L2224/45671 ,  H01L2224/45672 ,  H01L2224/45684 ,  H01L2224/45686 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48472 ,  H01L2224/48818 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48866 ,  H01L2224/48869 ,  H01L2224/48871 ,  H01L2224/48872 ,  H01L2224/48884 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2224/8592 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/20103 ,  H01L2924/351 ,  H01L2924/00015 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/01202 ,  H01L2924/20107 ,  H01L2924/20106 ,  H01L2224/29099 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01049

摘要： It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode 3) on a power semiconductor die 2 and another metal electrode (connection electrode 4) are connected by metal wire 5 using wedge bonding connection, the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 μm and not greater than 2 mm and the die 3 has thereon one or more metal and/or alloy layers, each of the layer(s) being 50 Å or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al.

摘要翻译： 本发明的目的是提供一种功率半导体器件，该功率半导体器件能够在不受热应力产生的情况下运行，从而减少线材的发热，确保当器件用于处理大的时候的接合部分的可靠性 量电流和/或在高温气氛下，制造该装置的方法和接合线。 在功率半导体器件中，功率半导体管芯2上的金属电极（管芯电极3）和另一个金属电极（连接电极4）通过金属线5使用楔形接合连接，金属线是Ag或Ag合金线 其直径大于50μm且不大于2mm，并且模具3上具有一个或多个金属和/或合金层，每个层的厚度均为50或更大，并且该层的金属 选自Ni，Cr，Cu，Pd，V，Ti，Pt，Zn，Ag，Au，W和Al。

公开(公告)号：US20150123253A1

公开(公告)日：2015-05-07

申请号：US14515700

申请日：2014-10-16

申请人： KEC Corporation

发明人： Kyu Hyo Hwang ,  Jong Hong Lee ,  Gab Soo Choi ,  Cha Soo Jeon ,  Jin Sang Park ,  Sang Bo Bae ,  Yong Min Park ,  Sung Jin An

IPC分类号： H01L23/00 ,  H01L23/495

CPC分类号： H01L23/49531 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05617 ,  H01L2224/0562 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05672 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/2912 ,  H01L2224/29123 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/83191 ,  H01L2224/83825 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/3651 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Provided are a semiconductor device and a bonding structure thereof, in which an inter-metal compound is not formed with a semiconductor die or a lead frame, thereby improving electrical and mechanical properties and wettability and suppressing conglomeration of a die bonding material. The semiconductor device includes a semiconductor die, a barrier layer formed on a surface of the semiconductor die, a first metal layer formed on the barrier layer, a central metal layer formed on the first metal layer, and a second metal layer formed on the central metal layer. Here, the first and second metal layers have a first melting temperature, and the central metal layer has a second melting temperature lower than the first melting temperature.

摘要翻译： 提供一种半导体器件及其接合结构，其中金属间化合物不形成半导体管芯或引线框架，从而提高电气和机械性能和润湿性并抑制管芯接合材料的聚集。 半导体器件包括半导体管芯，形成在半导体管芯的表面上的阻挡层，形成在阻挡层上的第一金属层，形成在第一金属层上的中心金属层，以及形成在中心上的第二金属层 金属层。 这里，第一和第二金属层具有第一熔融温度，并且中心金属层具有低于第一熔融温度的第二熔融温度。

公开(公告)号：US08922014B2

公开(公告)日：2014-12-30

申请号：US14086851

申请日：2013-11-21

申请人： Broadcom Corporation

发明人： Kevin (Kunzhong) Hu ,  Chonghua Zhong ,  Edward Law

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L21/561 ,  H01L21/76801 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2224/05552 ,  H01L2924/00

摘要： There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

摘要翻译： 这里公开了改进的晶片级半导体封装的各种实现方式。 一个示例性实现包括在固定在晶片表面上的第一和第二电介质层之间形成后制造再分配层（后Fab RDL），并形成用于接收第二介电层中的电接触体的窗口，窗口暴露 后Fab RDL。 第一和第二电介质层中的至少一个是预先形成的电介质层，其可以使用层压工艺固定在晶片的表面上。 在一个实施方案中，窗口使用直接激光烧蚀工艺形成。

公开(公告)号：US20140084462A1

公开(公告)日：2014-03-27

申请号：US14086851

申请日：2013-11-21

申请人： Broadcom Corporation

发明人： Kevin (Kunzhong) Hu ,  Chonghua Zhong ,  Edward Law

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L21/561 ,  H01L21/76801 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2224/05552 ,  H01L2924/00

摘要： There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

摘要翻译： 这里公开了改进的晶片级半导体封装的各种实现方式。 一个示例性实现包括在固定在晶片表面上的第一和第二电介质层之间形成后制造再分配层（后Fab RDL），并形成用于接收第二介电层中的电接触体的窗口，窗口暴露 后Fab RDL。 第一和第二电介质层中的至少一个是预先形成的电介质层，其可以使用层压工艺固定在晶片的表面上。 在一个实施方案中，窗口使用直接激光烧蚀工艺形成。

公开(公告)号：US20130292820A1

公开(公告)日：2013-11-07

申请号：US13718311

申请日：2012-12-18

申请人： SK HYNIX INC.

发明人： Tae Min KANG

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05026 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05672 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

摘要： Electronic device packages and related methods are provided. The electronic device package includes a first substrate having a first contact portion disposed thereon, a bump having a first contact surface connected to the first contact portion and a second contact surface disposed opposite to the first contact surface, and a buffer spring pad portion between the first contact portion of the first substrate and the first contact surface of the bump. The buffer spring pad portion includes at least two different conductive material layers which are stacked.

摘要翻译： 提供电子设备包装和相关方法。 电子器件封装包括具有设置在其上的第一接触部分的第一基板，具有连接到第一接触部分的第一接触表面的凸块和与第一接触表面相对设置的第二接触表面，以及缓冲弹簧垫部分 第一基板的第一接触部分和凸块的第一接触表面。 缓冲弹簧垫部分包括堆叠的至少两个不同的导电材料层。

公开(公告)号：US08461679B2

公开(公告)日：2013-06-11

申请号：US13108743

申请日：2011-05-16

申请人： Jin-Yuan Lee ,  Chien-Kang Chou ,  Shih-Hsiung Lin ,  Hsi-Shan Kuo

发明人： Jin-Yuan Lee ,  Chien-Kang Chou ,  Shih-Hsiung Lin ,  Hsi-Shan Kuo

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L24/11 ,  H01L24/13 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/013

摘要： A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.

摘要翻译： 圆柱形粘结结构及其制造方法。 在硅芯片的接合焊盘上形成圆柱形接合结构，并且在形成倒装芯片封装的过程中将芯片翻转以与衬底板连接。 圆柱形接合结构主要包括导电柱和焊帽。 导电柱形成在硅芯片的接合焊盘上，并且焊接帽附接到导电柱的上端。 焊锡帽的熔点低于导电柱。 焊帽可以被配置成圆柱形，球形或半球形。 为了制造圆柱形接合结构，在硅晶片上形成具有与位于晶片上的接合焊盘相对应的多个开口的图案化掩模层。 导电材料沉积到开口中以形成导电柱，最后在每个导电柱的末端附着焊帽。