公开(公告)号：US20180337144A1

公开(公告)日：2018-11-22

申请号：US16050117

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chun Miao ,  Shih-Wei Liang ,  Kai-Chiang Wu

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31

CPC classification number: H01L23/564 ,  H01L23/16 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/03828 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81466 ,  H01L2224/81471 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2224/81 ,  H01L2224/03

Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

公开(公告)号：US20170317044A1

公开(公告)日：2017-11-02

申请号：US15651063

申请日：2017-07-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/118 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/15788 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

公开(公告)号：US09230949B2

公开(公告)日：2016-01-05

申请号：US14641351

申请日：2015-03-07

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/495 ,  H01L25/07 ,  H01L23/492 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/367 ,  H01L25/065 ,  H01L23/433

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/27 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/07 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/118 ,  H01L2224/13022 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the metal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

Abstract translation: 堆叠多芯片封装结构包括引线框架，安装在引线框架上的第一半导体芯片，安装在引线框架上的第二半导体芯片翻转芯片，安装在第一和第二半导体芯片顶部的金属夹子和 第三半导体芯片堆叠在金属夹上; 将第三半导体芯片上的电极电连接到第一和第二半导体芯片和引线框架的引脚的接合线; 塑料成型封装引线框架，芯片和金属夹。

公开(公告)号：US20150262949A1

公开(公告)日：2015-09-17

申请号：US14259432

申请日：2014-04-23

Applicant: LSI Corporation

Inventor： John W. Osenbach ,  Steven D. Cate

IPC: H01L23/00

CPC classification number: H01L21/00 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/118 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81447 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/37 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/206 ,  H01L2224/03

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and first openings in the photoresist are formed. Metal layers are formed by electroplating metal into the first openings for a first time period. Then the photoresist is patterned to form second openings having a smaller diameter than the first openings. Narrow pillars are formed by electroplating metal into the second openings for a second time period during which the metal is also added to the metal layers in the first openings to form wide pillars having substantially the same height as the narrow pillars. The photoresist is then removed along with conductive layers on the device used as part of the plating process.

Abstract translation: 一种在倒装芯片上形成金属柱的工艺。 支柱以及一层焊料将用于将器件上的管芯焊盘与衬底上相应的衬底焊盘接合。 光致抗蚀剂沉积在器件上，并形成光致抗蚀剂中的第一个开口。 金属层通过将金属电镀第一次开始形成。 然后将光致抗蚀剂图案化以形成具有比第一开口小的直径的第二开口。 通过将金属电镀到第二开口中第二时间段来形成窄柱，在此期间金属也被添加到第一开口中的金属层，以形成具有与窄柱基本相同的高度的宽支柱。 然后将光致抗蚀剂与用作电镀工艺的一部分的器件上的导电层一起除去。

公开(公告)号：US20130140691A1

公开(公告)日：2013-06-06

申请号：US13312730

申请日：2011-12-06

Applicant: Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

Inventor： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

IPC: H01L23/498 ,  H01L21/28

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0332 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/035 ,  H01L2224/03505 ,  H01L2224/0361 ,  H01L2224/03632 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05086 ,  H01L2224/05088 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11466 ,  H01L2224/118 ,  H01L2224/11849 ,  H01L2224/11916 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/01013 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00013 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/04941 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

公开(公告)号：US11862574B2

公开(公告)日：2024-01-02

申请号：US17369413

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Soo Kim

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L21/568 ,  H01L24/13 ,  H01L2224/118 ,  H01L2224/13101 ,  H01L2224/18 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00012 ,  H01L2924/1431 ,  H01L2924/00012 ,  H01L2924/1436 ,  H01L2924/1433 ,  H01L2924/00012

Abstract: A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filing at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.

公开(公告)号：US09159687B2

公开(公告)日：2015-10-13

申请号：US13572302

申请日：2012-08-10

Applicant: Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/118 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/15788 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

Abstract translation: 用于球栅阵列（BGA）的焊料凸块结构包括在至少一个UBM层上形成的至少一个下凸块金属（UBM）层和焊料凸块。 焊料凸块具有凸块宽度和凸块高度，并且凸块高度比凸块宽度的比值小于1。

公开(公告)号：US08836118B2

公开(公告)日：2014-09-16

申请号：US13718311

申请日：2012-12-18

Applicant: SK hynix Inc.

Inventor： Tae Min Kang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/48 ,  H01L21/768 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05026 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05672 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Electronic device packages and related methods are provided. The electronic device package includes a first substrate having a first contact portion disposed thereon, a bump having a first contact surface connected to the first contact portion and a second contact surface disposed opposite to the first contact surface, and a buffer spring pad portion between the first contact portion of the first substrate and the first contact surface of the bump. The buffer spring pad portion includes at least two different conductive material layers which are stacked.

Abstract translation: 提供电子设备包装和相关方法。 电子器件封装包括具有设置在其上的第一接触部分的第一基板，具有连接到第一接触部分的第一接触表面的凸块和与第一接触表面相对设置的第二接触表面，以及缓冲弹簧垫部分 第一基板的第一接触部分和凸块的第一接触表面。 缓冲弹簧垫部分包括堆叠的至少两个不同的导电材料层。

公开(公告)号：US08227334B2

公开(公告)日：2012-07-24

申请号：US12843760

申请日：2010-07-26

Applicant: Ming-Da Cheng ,  Ming-Che Ho ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Cheng-Chung Lin ,  Hui-Jung Tsai ,  Zheng-Yi Lim

Inventor： Ming-Da Cheng ,  Ming-Che Ho ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Cheng-Chung Lin ,  Hui-Jung Tsai ,  Zheng-Yi Lim

IPC: H01L21/00

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11416 ,  H01L2224/11422 ,  H01L2224/11424 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11822 ,  H01L2224/11827 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/132 ,  H01L2224/13211 ,  H01L2224/13339 ,  H01L2224/13562 ,  H01L2224/13584 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/1379 ,  H01L2224/13794 ,  H01L2224/13809 ,  H01L2224/13813 ,  H01L2224/13817 ,  H01L2224/13818 ,  H01L2224/1382 ,  H01L2224/13849 ,  H01L2224/13855 ,  H01L2224/13857 ,  H01L2224/1386 ,  H01L2224/13866 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/93 ,  H01L2225/06513 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Abstract translation: 形成器件的方法包括提供衬底，以及在衬底上形成焊料凸点。 将次要元件引入邻近焊料凸块顶表面的区域。 然后对焊料凸块执行再流程以将次要元件驱动到焊料凸块中。

公开(公告)号：US07829453B2

公开(公告)日：2010-11-09

申请号：US11531437

申请日：2006-09-13

Applicant: Gotthard Jungnickel ,  Alexander Platz ,  Frank Kuechenmeister

Inventor： Gotthard Jungnickel ,  Alexander Platz ,  Frank Kuechenmeister

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81011 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/3457 ,  H05K3/3494 ,  H05K2203/0315 ,  H05K2203/043 ,  H05K2203/086 ,  H01L2924/00014

Abstract: By controlling the cooling rate during the oxidation process for forming an oxide layer on solder balls and by selecting an elevated temperature as an initial temperature of the oxidation process, a reliable yet easily removable oxide layer may be obtained. Consequently, yield losses during the flip chip assembly process may be significantly reduced.

Abstract translation: 通过控制用于在焊球上形成氧化物层的氧化过程中的冷却速度，并且通过选择升高的温度作为氧化工艺的初始温度，可以获得可靠且容易移除的氧化物层。 因此，倒装芯片组装过程中的屈服损失可能会显着降低。