公开(公告)号：US09502388B2

公开(公告)日：2016-11-22

申请号：US15017666

申请日：2016-02-07

Applicant: Renesas Electronics Corporation

Inventor： Takamitsu Kanazawa ,  Satoru Akiyama

IPC: H01L29/15 ,  H01L31/0312 ,  H01L25/07 ,  H01L21/82 ,  H01L27/02 ,  H01L27/088 ,  H01L23/495 ,  H01L29/16 ,  H01L27/06 ,  H01L29/808 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L25/072 ,  H01L21/8213 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/808 ,  H01L29/8083 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/3702 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40105 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/84

Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.

Abstract translation: 提供了能够提高半导体器件的可靠性的技术。 在本发明中，形成在半导体芯片CHP1的前表面上的栅极焊盘GPj被布置成比其他引线（漏极引线DL和栅极引线GL）更靠近源极引线SL。 结果，根据本发明，可以缩短栅极焊盘GPj和源极引线SL之间的距离，从而可以缩短用于将栅极焊盘GPj和源极引线SL连接在一起的焊丝Wgj的长度。 因此，根据本发明，可以充分地减小存在于导线Wgj中的寄生电感。

公开(公告)号：US09373571B2

公开(公告)日：2016-06-21

申请号：US14938387

申请日：2015-11-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L25/18 ,  H01L23/495 ,  H01L23/00 ,  H01L21/50 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively. The common terminal is connected by a common clip to a substrate pin.

Abstract translation: 电子多输出装置具有包括第一垫，第二垫和多个销的基板。 具有第一晶体管的第一芯片在一个芯片表面上具有第一端子，在相对的芯片表面上具有第二和第三端子。 第一个芯片与第一个终端绑在第一个焊盘上。 具有第二晶体管的第二芯片在一个芯片表面上具有第一端子，在相对的芯片表面上具有第二和第三端子。 具有第一个终端的第二个芯片与第二个焊盘相连。 第二端子通过离散的第一金属夹和第二金属夹连接到相应的衬底引脚。 复合第三芯片具有集成的晶体管的第一端子在一个芯片表面上的第三和第四晶体管。 第二个终端被合并成一个公共终端。 图案化的第三端子在相对的芯片表面上。 第一端子分别垂直地附接到第一和第二金属夹。 公共端子通过公共夹子连接到基板引脚。

公开(公告)号：US09142503B2

公开(公告)日：2015-09-22

申请号：US14333401

申请日：2014-07-16

Applicant: International Rectifier Corporation

Inventor： Chuan Cheah ,  Dae Keun Park

IPC: H01L21/331 ,  H01L21/60 ,  H01L23/498 ,  H01L23/495 ,  H01L25/18 ,  H03K17/567 ,  H03K17/687 ,  H03K17/74 ,  H01L23/00 ,  H01L21/56 ,  H01L25/07 ,  H01L29/20 ,  H01L29/778 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L23/49844 ,  H01L21/56 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/97 ,  H01L25/074 ,  H01L25/18 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/06181 ,  H01L2224/32145 ,  H01L2224/37147 ,  H01L2224/40145 ,  H01L2224/40225 ,  H01L2224/73263 ,  H01L2224/92246 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/15787 ,  H03K17/567 ,  H03K17/687 ,  H03K17/74 ,  H03K2017/6875 ,  H01L2224/84 ,  H01L2224/83 ,  H01L2924/00

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

Abstract translation: 已经公开了利用封装支撑表面上的夹子的高压级联III族氮化物半导体封装的一些示例性实施例。 一个示例性实施例包括附接到封装支撑表面并具有堆叠在III族氮化物晶体管的源极上的二极管的阳极的III族氮化物晶体管，耦合到III族氮化物晶体管的栅极的第一导电夹和阳极 并且耦合到III族氮化物晶体管的漏极的第二导电夹。 导电夹子连接到封装支撑表面并暴露出可表面安装的相应的平坦部分。 以这种方式，与传统的导线接合封装相比，可以实现减小的封装占地面积，改进的浪涌电流能力和更高的性能。 此外，由于可以将低成本印刷电路板（PCB）用于封装支撑表面，因此可以避免昂贵的无引线制造工艺以实现成本有效的制造。

公开(公告)号：US20140327014A1

公开(公告)日：2014-11-06

申请号：US14333401

申请日：2014-07-16

Applicant: International Rectifier Corporation

Inventor： Chuan Cheah ,  Dae Keun Park

IPC: H01L23/498

CPC classification number: H01L23/49844 ,  H01L21/56 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/97 ,  H01L25/074 ,  H01L25/18 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/06181 ,  H01L2224/32145 ,  H01L2224/37147 ,  H01L2224/40145 ,  H01L2224/40225 ,  H01L2224/73263 ,  H01L2224/92246 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/15787 ,  H03K17/567 ,  H03K17/687 ,  H03K17/74 ,  H03K2017/6875 ,  H01L2224/84 ,  H01L2224/83 ,  H01L2924/00

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

Abstract translation: 已经公开了利用封装支撑表面上的夹子的高压级联III族氮化物半导体封装的一些示例性实施例。 一个示例性实施例包括附接到封装支撑表面并具有堆叠在III族氮化物晶体管的源极上的二极管的阳极的III族氮化物晶体管，耦合到III族氮化物晶体管的栅极的第一导电夹和阳极 并且耦合到III族氮化物晶体管的漏极的第二导电夹。 导电夹子连接到封装支撑表面并暴露出可表面安装的相应的平坦部分。 以这种方式，与传统的导线接合封装相比，可以实现减小的封装占地面积，改进的浪涌电流能力和更高的性能。 此外，由于可以将低成本印刷电路板（PCB）用于封装支撑表面，因此可以避免昂贵的无引线制造工艺以实现成本有效的制造。

公开(公告)号：US11908780B2

公开(公告)日：2024-02-20

申请号：US17518554

申请日：2021-11-03

Applicant: Texas Instruments Incorporated

Inventor： Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Lance Cole Wright ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/074 ,  H01L25/16 ,  H01L25/50 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40145 ,  H01L2224/40177 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/83815 ,  H01L2224/84815 ,  H01L2224/92246 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/2064

Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

公开(公告)号：US20150179626A1

公开(公告)日：2015-06-25

申请号：US14641351

申请日：2015-03-07

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

IPC: H01L25/00 ,  H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L23/367 ,  H01L21/304 ,  H01L21/66 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/27 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/07 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/118 ,  H01L2224/13022 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the metal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

Abstract translation: 堆叠多芯片封装结构包括引线框架，安装在引线框架上的第一半导体芯片，安装在引线框架上的第二半导体芯片翻转芯片，安装在第一和第二半导体芯片顶部的金属夹子和 第三半导体芯片堆叠在金属夹上; 将第三半导体芯片上的电极电连接到第一和第二半导体芯片和引线框架的引脚的接合线; 塑料成型封装引线框架，芯片和金属夹。

公开(公告)号：US20150035129A1

公开(公告)日：2015-02-05

申请号：US13955206

申请日：2013-07-31

Applicant: Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

Inventor： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/27 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/07 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/118 ,  H01L2224/13022 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

Abstract translation: 堆叠多芯片封装结构包括引线框架，安装在引线框架上的第一半导体芯片，安装在引线框架上的第二半导体芯片翻转芯片，安装在第一和第二半导体芯片顶部的金属夹子和 第三个半导体芯片堆叠在餐夹上; 将第三半导体芯片上的电极电连接到第一和第二半导体芯片和引线框架的引脚的接合线; 塑料成型封装引线框架，芯片和金属夹。

公开(公告)号：US20140231829A1

公开(公告)日：2014-08-21

申请号：US14348048

申请日：2011-09-30

Applicant: Takamitsu Kanazawa ,  Satoru Akiyama

Inventor： Takamitsu Kanazawa ,  Satoru Akiyama

IPC: H01L27/06 ,  H01L29/16

CPC classification number: H01L25/072 ,  H01L21/8213 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/808 ,  H01L29/8083 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/3702 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40105 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/84

Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.

Abstract translation: 提供了能够提高半导体器件的可靠性的技术。 在本发明中，形成在半导体芯片CHP1的前表面上的栅极焊盘GPj被布置成比其他引线（漏极引线DL和栅极引线GL）更靠近源极引线SL。 结果，根据本发明，可以缩短栅极焊盘GPj和源极引线SL之间的距离，从而可以缩短用于将栅极焊盘GPj和源极引线SL连接在一起的焊丝Wgj的长度。 因此，根据本发明，可以充分地减小存在于导线Wgj中的寄生电感。

公开(公告)号：US08039959B2

公开(公告)日：2011-10-18

申请号：US11580750

申请日：2006-10-13

Applicant: Masud Beroz

Inventor： Masud Beroz

IPC: H01L23/48

CPC classification number: H01L23/49805 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02379 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/401 ,  H01L2224/40145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48149 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2224/73213 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A microelectronic connection component includes a substrate having a first surface, a second surface and a peripheral edge. First and second terminals are exposed at the first surface of the substrate. Wire bond pads are exposed proximate the peripheral edge of the substrate at the first surface. First conductive paths couple the first terminals to the wire bond pads. Bonding leads extend beyond the peripheral edge of the substrate. Second conductive paths couple the second terminals to the bonding leads.

Abstract translation: 微电子连接部件包括具有第一表面，第二表面和外围边缘的基板。 第一和第二端子在基板的第一表面处露出。 引线接合焊盘在第一表面附近暴露于基板的周边边缘。 第一导电路径将第一端子耦合到引线接合焊盘。 接合引线延伸超过衬底的周缘。 第二导电路径将第二端子耦合到接合引线。

公开(公告)号：US09355991B2

公开(公告)日：2016-05-31

申请号：US14938465

申请日：2015-11-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L21/50 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips. The third terminals are concurrently attached by discrete gang clips to respective pins. A common clip is attached to the common second terminal and connecting the common clip to a pin.

Abstract translation: 一种制造电子多输出装置的方法。 提供具有焊盘和引脚的基板。 提供第一芯片，其具有集成的第一和第二晶体管，使得晶体管的第一端子在一个芯片表面上合并成公共端子，并且图案化的第二和第三端子在相对的芯片表面上。 公共第一端子附接到衬底垫。 驱动器和控制芯片附接到与第一芯片相邻的衬底焊盘。 第一和第二晶体管的第二端子通过离散的第一和第二组合夹连接到相应的衬底引脚。 提供第二芯片，其具有集成的第三和第四晶体管，使得晶体管的第二端子在一个芯片表面上合并成公共端子。 图案化的第一和第三端子在相对的芯片表面上。 第二芯片被翻转以将第一终端垂直地附接到第一和第二组合夹。 第三端子通过离散的组夹同时附接到相应的引脚。 共同的夹子连接到公共第二端子并将公共夹子连接到销。