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    Power Semiconductor Device with Source Trench and Termination Trench Implants
    4.
    发明申请
    Power Semiconductor Device with Source Trench and Termination Trench Implants 有权
    具有源沟槽和端接沟槽植入物的功率半导体器件

    公开(公告)号：US20160104766A1

    公开(公告)日：2016-04-14

    申请号：US14856241

    申请日：2015-09-16

    Applicant: International Rectifier Corporation

    Inventor： Kapil Kelkar ,  Timothy D. Henson ,  Ling Ma ,  Mary Bigglestone ,  Adam Amali ,  Hugo Burke ,  Robert Haase

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

    CPC classification number: H01L29/0623 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

    Abstract: A power semiconductor device is disclosed. The power semiconductor device includes a source region in a body region, a gate trench adjacent to the source region, and a source trench electrically coupled to the source region. The source trench includes a source trench conductive filler surrounded by a source trench dielectric liner, and extends into a drift region. The power semiconductor device includes a source trench implant below the source trench and a drain region below the drift region, where the source trench implant has a conductivity type opposite that of the drift region. The power semiconductor device may also include a termination trench adjacent to the source trench, where the termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner. The power semiconductor device may also include a termination trench implant below the termination trench.

    Abstract translation: 公开了功率半导体器件。 功率半导体器件包括体区中的源极区域，与源极区域相邻的栅极沟槽，以及电耦合到源极区域的源极沟槽。 源极沟槽包括由源极沟槽电介质衬垫围绕并且延伸到漂移区域中的源极沟槽导电填料。 功率半导体器件包括源极沟槽下方的源沟槽注入和漂移区下方的漏极区，其中源极沟槽注入具有与漂移区相反的导电类型。 功率半导体器件还可以包括与源沟槽相邻的端接沟槽，其中端接沟槽包括由终端沟槽电介质衬垫围绕的终端沟槽导电填料。 功率半导体器件还可以包括在端接沟槽下方的端接沟槽注入。

    Fault and Short-Circuit Protected Output Driver
    6.
    发明申请
    Fault and Short-Circuit Protected Output Driver 有权
    故障和短路保护输出驱动器

    公开(公告)号：US20160087422A1

    公开(公告)日：2016-03-24

    申请号：US14845638

    申请日：2015-09-04

    Applicant: International Rectifier Corporation

    Inventor： Andre Mourrier ,  Vincent Thiery ,  Vincent Laville ,  Loic Bourguine

    IPC: H02H3/10 ,  H03K17/082

    CPC classification number: H03K17/082 ,  H02H3/08 ,  H02H3/202 ,  H02H7/0844 ,  H02H7/122 ,  H02M7/5387 ,  H03K17/284

    Abstract: A driver and protection circuit for driving a power switch is disclosed. The driver and protection circuit includes a fault detection block configured to detect a discrepancy between a reference drive signal and a measured voltage at a gate of the power switch. The driver and protection circuit also includes a short circuit detection block configured to detect a gate-to-source short circuit or a gate-to-drain short circuit of the power switch. The driver and protection circuit further includes a latch coupled to the fault detection block and the short circuit detection block to selectively turn off an output driver coupled to the gate of the power switch when a fault or a short circuit is detected, and wherein the latch is configured to send a diagnostic signal when the fault or the short circuit is detected.

    Abstract translation: 公开了用于驱动电源开关的驱动器和保护电路。 驱动器和保护电路包括故障检测块，其被配置为检测参考驱动信号和电源开关门的测量电压之间的差异。 驱动器和保护电路还包括被配置为检测电源开关的栅极到源极短路或栅极到漏极短路的短路检测块。 驱动器和保护电路还包括耦合到故障检测块的锁存器和短路检测块，以在检测到故障或短路时选择性地关闭耦合到电源开关的栅极的输出驱动器，并且其中锁存器 被配置为当检测到故障或短路时发送诊断信号。

    Enhancement Mode III-Nitride Transistor
    9.
    发明申请
    Enhancement Mode III-Nitride Transistor 有权
    增强型III型氮化物晶体管

    公开(公告)号：US20150333165A1

    公开(公告)日：2015-11-19

    申请号：US14813042

    申请日：2015-07-29

    Applicant: International Rectifier Corporation

    Inventor： Michael A. Briere

    IPC: H01L29/778 ,  H01L29/205

    CPC classification number: H01L29/7783 ,  H01L21/02063 ,  H01L21/76814 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4232 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/803

    Abstract: According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.

    Abstract translation: 根据一个实施例，III族氮化物晶体管包括在第一和第二III族氮化物体之间形成的导电通道，该导电通道包括二维电子气。 所述晶体管还包括至少一个具有限制在其中的电荷的栅介质层，以引起导通通道的中断区域，以及可操作以恢复导通通道的中断区域的栅电极。 晶体管可以是增强型晶体管。 在一个实施例中，栅介质层是氮化硅层。 在另一个实施例中，至少一个栅介质层是氧化硅层。 电荷可以离子注入到至少一个栅极电介质层中。 至少一个栅介电层也可以与电荷一起生长。

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