公开(公告)号：US20180261568A1

公开(公告)日：2018-09-13

申请号：US15978043

申请日：2018-05-11

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Ruby Ann Maya Merto ,  Jerry Gomez Cayabyab ,  Edsel Gomez Balagtas

IPC分类号： H01L23/00

CPC分类号： H01L24/78 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/77 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/77704 ,  H01L2224/78301 ,  H01L2224/78704 ,  H01L2224/78744 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/20751 ,  H01L2924/00015 ,  H01L2224/37099

摘要： A wire bonding machine window clamp assembly. The assembly includes a support plate adapted to support a leadframe strip. The assembly also includes a frame structure defining a central clamp opening adapted to expose a portion of the leadframe strip. The frame structure includes at least one elongate frame member having a first surface portion adapted to engage a top surface of the leadframe strip and a second surface portion adapted to engage upper surfaces of integrated circuit (“IC”) component stacks mounted on the leadframe strip.

公开(公告)号：US20180166377A1

公开(公告)日：2018-06-14

申请号：US15890482

申请日：2018-02-07

申请人： Tesla, Inc.

发明人： Wenjun Liu ,  Robert James Ramm ,  Colin Kenneth Campbell

IPC分类号： H01L23/50 ,  H01L49/02 ,  H01G4/12 ,  H01L23/373

CPC分类号： H01L23/50 ,  H01G4/12 ,  H01L21/4825 ,  H01L23/057 ,  H01L23/3735 ,  H01L23/49534 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L25/072 ,  H01L28/40 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/37099 ,  H01L2224/37599 ,  H01L2224/40 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/014

摘要： A semiconductor device includes housing, a substrate, a first semiconductor die, a second semiconductor die, a first terminal, and a second terminal. The first terminal in a first terminal plane couples to the first semiconductor die. The second terminal has a contact portion in a contact portion plane within the housing that couples to the second semiconductor die, a main portion in a main portion plane partially within the housing, the main portion plane substantially parallel to and offset from the first terminal plane, and the main portion plane substantially parallel to and offset from the contact portion plane, and an offsetting portion within the housing and that connects the contact portion to the main portion. At least some of the main portion of the second terminal overlaps the first terminal and the first terminal and the main portion of the second terminal extend from the housing in a same direction.

公开(公告)号：US09818687B2

公开(公告)日：2017-11-14

申请号：US15177658

申请日：2016-06-09

申请人： Fuji Electric Co., Ltd.

发明人： Naoyuki Kanai

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/24 ,  H01L23/60 ,  H01L23/373 ,  H01L23/00 ,  H01L25/07 ,  H01L23/14

CPC分类号： H01L23/49894 ,  H01L21/4871 ,  H01L21/563 ,  H01L23/053 ,  H01L23/142 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/60 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/45 ,  H01L24/73 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/40137 ,  H01L2224/40227 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/4516 ,  H01L2224/45565 ,  H01L2224/45624 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/2076 ,  H01L2224/37099

摘要： A semiconductor module includes an insulated circuit board that includes an insulating substrate, a first conductive plate arranged on a first principal surface of the insulating substrate and within the outer edges of the insulating substrate, and a second conductive plate arranged within the outer edges of the insulating substrate on a second principal surface of the insulating substrate that faces the first principal surface. Furthermore, boundary edges between the first principal surface of the insulating substrate and the side faces of the first conductive plate are covered by an ion gel that contains an ionic liquid.

公开(公告)号：US09812383B2

公开(公告)日：2017-11-07

申请号：US14920424

申请日：2015-10-22

申请人： Infineon Technologies Americas Corp.

发明人： Eung San Cho ,  Dan Clavette

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/34 ,  H01L23/00 ,  H01L25/07 ,  H02M3/158

CPC分类号： H01L23/49562 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H02M3/158 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/37099 ,  H01L2224/84

摘要： A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

公开(公告)号：US09799586B2

公开(公告)日：2017-10-24

申请号：US14919653

申请日：2015-10-21

申请人： Infineon Technologies Americas Corp.

发明人： Eung San Cho ,  Dan Clavette

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/34 ,  H01L23/00 ,  H01L25/07 ,  H02M3/158

CPC分类号： H01L23/49562 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H02M3/158 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/37099 ,  H01L2224/84

摘要： A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

公开(公告)号：US09780059B2

公开(公告)日：2017-10-03

申请号：US14339524

申请日：2014-07-24

申请人： Semiconductor Components Industries, LLC

发明人： Shutesh Krishnan ,  Yun Sung Won

IPC分类号： H01L23/00 ,  H01L23/495

CPC分类号： H01L24/27 ,  H01L23/49513 ,  H01L23/49524 ,  H01L24/16 ,  H01L24/29 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/27334 ,  H01L2224/29 ,  H01L2224/29006 ,  H01L2224/29101 ,  H01L2224/29199 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/8184 ,  H01L2224/83048 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/838 ,  H01L2224/8384 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/37099 ,  H01L2224/05599

摘要： A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

公开(公告)号：US20170271304A1

公开(公告)日：2017-09-21

申请号：US15457790

申请日：2017-03-13

申请人： VISHAY-SILICONIX

发明人： Frank Kuo ,  Suresh Belani

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

摘要： A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

公开(公告)号：US09761501B2

公开(公告)日：2017-09-12

申请号：US14783851

申请日：2013-04-11

申请人： Renesas Electronics Corporation

发明人： Toshitsugu Ishii ,  Naohiro Makihira ,  Hidekazu Iwasaki ,  Jun Matsuhashi

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L25/00 ,  G01R31/40 ,  G01R1/067 ,  G01R31/28 ,  G01R1/04

CPC分类号： H01L22/14 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/06738 ,  G01R31/2874 ,  G01R31/40 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.

公开(公告)号：US09748165B2

公开(公告)日：2017-08-29

申请号：US15052899

申请日：2016-02-25

申请人： DELTA ELECTRONICS, INC.

发明人： Hsin-Chang Tsai ,  Peng-Hsin Lee

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L25/07 ,  H01L23/00 ,  H01L23/433

CPC分类号： H01L23/49541 ,  H01L23/3114 ,  H01L23/4334 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/40 ,  H01L25/072 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2224/37099

摘要： A packaging structure includes a lead frame, a chip, and a packaging material. The lead frame has a pair of opposed first surface and second surface, and has a first recessed region located on the second surface. The chip has a pair of opposed first surface and second surface. The first surface of the chip is fixed on the first recessed region. The packaging material surrounds the lead frame and the chip. The second surface of the chip is exposed from the packaging material, and the first surface of the lead frame is exposed from the packaging material.

公开(公告)号：US09742108B2

公开(公告)日：2017-08-22

申请号：US15238911

申请日：2016-08-17

申请人： Sumitomo Wiring Systems, Ltd.

发明人： Junya Matsuura

IPC分类号： H01R13/627 ,  H01R13/11 ,  H01L23/00 ,  H01R13/66 ,  H01R103/00

CPC分类号： H01R13/6272 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/37599 ,  H01L2924/00014 ,  H01R13/113 ,  H01R13/6641 ,  H01R2103/00 ,  H01L2224/37099 ,  H01L2224/84

摘要： A connector is configured such that a fitting-side component (10) is fit into a receiving-side component (20). The fitting-side component (10) includes a block-shaped main body (11) and a lock (15) standing on an outer surface of the main body (11). The receiving-side component (20) includes a receptacle (21) open forward and externally fittable to the fitting-side component (10). A locking surface (16) is provided on a surface of the lock (15) facing an opening side of the receptacle (21) in a fitted state of the fitting-side component (10) and the receiving-side component (20). The locking surface (16) stands substantially at a right angle to a separating direction from the receiving-side component (20). The receiving-side component (20) includes a lock projection (35) projecting on an inner surface of the receptacle (21) for locking the locking surface 16 from the opening side of the receptacle (21).