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公开(公告)号：US20240361379A1
公开(公告)日：2024-10-31
申请号：US18767964
申请日：2024-07-09
Applicant: HITOP INSTRUMENT (JIANGSU) CO., LTD.
Inventor： Dongxi LIU
IPC: G01R31/28
CPC classification number: G01R31/2874 , G01R31/2875 , G01R31/2877
Abstract: A small-sized fast cold and hot shock test device is provided. The device includes a host, a test head used for cold and hot shock to a component under test by temperature control and output of compressed air, and an adjustment device for adjusting a position of the test head. The host includes a control device at least used to send temperature control data to the test head. The test head includes an eddy current mechanism for cooling or heating the compressed air, a heater including an air inlet end and an air outlet end, and a nozzle. The eddy current mechanism includes an air inlet, a cold air outlet, and a hot air outlet. The air inlet is connected with an air supply system through an intake air line unit. The cool air outlet is connected with the air inlet end of the heater.
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公开(公告)号：US20240337685A1
公开(公告)日：2024-10-10
申请号：US18298249
申请日：2023-04-10
Applicant: Teledyne LeCroy, Inc.
Inventor： Matthew Weinstein , Francois Lamarche , Lawrence Jacobs
IPC: G01R31/28 , G01R31/302
CPC classification number: G01R31/2874 , G01R31/3025
Abstract: A receiver comprising a magnitude correction circuit to receive an electrical signal defined by a phase. The electrical signal is a combined electrical signal comprising a first signal and a second signal. The magnitude correction circuit comprising a detector to generate a control signal proportional to received power of the second signal and an error amplifier coupled to the detector to compare a reference voltage against an output of the detector to determine an amplification or attenuation of the second signal based on a drift of the electrical signal. The receiver further comprising a variable gain amplifier coupled to the magnitude correction circuit to generate a compensated electrical signal based on the amplification or attenuation of the second signal determined by the magnitude correction circuit and a de-modulating mixer coupled to the magnitude correction circuit, the de-modulating mixer to mix a phase compensated signal and the compensated electrical signal.
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公开(公告)号：US12112964B2
公开(公告)日：2024-10-08
申请号：US17679158
申请日：2022-02-24
Applicant: Sheng-Hung Wang , Po-Hsiang Chang , Zhe-Min Liao
Inventor： Sheng-Hung Wang , Po-Hsiang Chang , Zhe-Min Liao
IPC: H01L21/673 , B25J15/06 , G01R31/28
CPC classification number: H01L21/67333 , B25J15/0616 , G01R31/2874 , G01R31/2893
Abstract: The invention provides a chip carrier, a chip testing module and a chip handling module. The chip carrier for carrying a plurality of chips comprises a main body with an upper surface and a lower surface. The main body has a plurality of air guide holes, and two ends of each air guide hole are respectively exposed on the upper surface and the lower surface. A part of the air guide holes are defined as a first group, and the air guide holes of the first group are connected. The main body is made of conductive material.
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公开(公告)号：US12111348B2
公开(公告)日：2024-10-08
申请号：US17483411
申请日：2021-09-23
CPC classification number: G01R31/2874 , H01L25/115 , H01L29/1608
Abstract: An evaluation module configured to evaluate the lifespan of a multichip module, the multichip module comprising a first substrate and multiple chips under evaluation, includes a second substrate, configured to be the same as the first substrate, and having attachment positions corresponding to the attachment positions on the first substrate, and at least one evaluation chip, configured to be the same as the multiple chips under evaluation. The number of evaluation chips is less than the number of chips under evaluation by at least one. The at least one evaluation chip is arranged at an attachment position on the second substrate, such that the at least one evaluation chip and the chip under evaluation arranged at the corresponding attachment position on the multichip module have the same cooling performance and sustain the same thermal stress. The present disclosure also discloses a method for evaluating the lifespan of a multichip module.
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公开(公告)号：US20240329118A1
公开(公告)日：2024-10-03
申请号：US18589423
申请日：2024-02-28
Applicant: Tokyo Seimitsu Co., Ltd.
Inventor： Hiroo TAMURA
IPC: G01R31/28 , G01R1/073 , H01L21/66 , H01L21/683
CPC classification number: G01R31/2874 , G01R1/07342 , H01L21/6831 , H01L22/14
Abstract: Provided with a prober and a temperature measurement method capable of achieving an automatization of a temperature measurement of a wafer chuck. A temperature measurement jig (70) having one or more temperature sensors (72) is supported at a position where a probe card is supported when the probe card is conveyed using a conveyance device configured to transfer the probe card to a wafer chuck (18), the temperature measurement jig having one or more temperature sensors, and the one or more temperature sensors is contacted with a surface of the wafer chuck to be measured in a state that the conveyance device supports the temperature measurement jig.
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Patent Agency Ranking
公开(公告)号：US20240295600A1
公开(公告)日：2024-09-05
申请号：US18427138
申请日：2024-01-30
Applicant: SEMIGHT INSTRUMENTS CO., LTD
Inventor： Zhe LIAN , Jianjun HUANG , Yonghong WU , Shan ZHAO , Haiyang HU
IPC: G01R31/28
CPC classification number: G01R31/2874 , G01R31/2856 , G01R31/2863 , G01R31/2867 , G01R31/2868 , G01R31/2896
Abstract: Chip testing device and package testing machine are provided. The chip testing device includes an upper base and a lower base, the upper base being above the lower base and being pressed against the lower base, and a top of the lower base featuring a first mounting part for mounting a test chip and a second mounting part beneath the first mounting part; a first test probe, penetrating the upper base and contacts the test chip to obtain an electrical signal of the test chip; a heat sink base, at the second mounting part and contacting the test chip to transfer a received heat to the test chip; and a first temperature sensor in the heat sink base to measure an actual temperature of the test chip.
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公开(公告)号：US20240280631A1
公开(公告)日：2024-08-22
申请号：US18290459
申请日：2021-05-21
Applicant: Mitsubishi Electric Corporation
Inventor： Yusuke YAMAKAJI , Masaomi WASHINO , Nobuyuki HARUNA
CPC classification number: G01R31/2879 , G01R1/06733 , G01R31/2874
Abstract: A signal generation unit outputs a first AC signal and a second AC signal having different phases as noise. A first coaxial cable transmits a first AC signal. A second coaxial cable transmits a second AC signal. A first probe is connected to the first coaxial cable and arranged in proximity to an IC on a printed circuit board to apply the first AC signal to the IC. A second probe is connected to the second coaxial cable and arranged in proximity to the IC to apply the second AC signal to the IC. A determination device determines whether the IC is malfunctioning, based on a state of the IC after application of the first AC signal and the second AC signal.
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公开(公告)号：US20240183898A1
公开(公告)日：2024-06-06
申请号：US18440226
申请日：2024-02-13
Applicant: Advantest Test Solutions, Inc.
Inventor： Karthik Ranganathan , Aritomo Kikuchi , Merlin Wallner , Rajan Surve , Samer Kabbani , Paul Ferrari , Ikeda Hiroki , Kiyokawa Toshiyuki , Gregory Cruzan , Todd Berk , Ian Williams , Mohammad Ghazvini , Thomas Jones
CPC classification number: G01R31/2875 , G01R1/0458 , G01R31/2863 , G01R31/2867 , G01R31/2874
Abstract: An active thermal interposer (ATI) device for use in testing integrated circuit device under test (DUT) having thermal isolation structures. The ATI device includes a formation having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the formation, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the formation is disposed adjacent to an interface surface of the DUT during testing of the DUT. The ATI device includes a plurality of thermal resistance structures configured to resist thermal conductance between the plurality of heating zones.
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公开(公告)号：US20240003967A1
公开(公告)日：2024-01-04
申请号：US18204309
申请日：2023-05-31
Applicant: Advantest Test Solutions, Inc.
Inventor： Samer Kabbani , Paul Ferrari , Ikeda Hiroki , Kiyokawa Toshiyuki , Gregory Cruzan , Karthik Ranganathan , Todd Berk , Ian Williams , Mohammad Ghazvini , Thomas Jones
CPC classification number: G01R31/2875 , G01R31/2867 , G01R31/2863 , G01R1/0458 , G01R31/2874
Abstract: A stand-alone active thermal interposer device for use in testing an unpackaged integrated circuit device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.
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公开(公告)号：US20230366923A1
公开(公告)日：2023-11-16
申请号：US18358458
申请日：2023-07-25
Applicant: Intel Corporation
Inventor： Sarah Shahraini , Mohamed Abdelmoneum , Richard Dorrance , Renzhi Liu , Eduardo Alban
CPC classification number: G01R31/2874 , G01R31/2879 , G06N20/00
Abstract: Systems, apparatuses and methods may provide for chip technology including a memory structure having stored weights associated with a machine learning (ML) model, a plurality of digital temperature sensors to generate readings, and a classification engine to retrieve the stored weights from the memory structure and adjust the readings from the plurality of digital temperature sensors based on the weights and electrical parameters associated with the chip.
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