公开(公告)号：US20240337694A1

公开(公告)日：2024-10-10

申请号：US18311870

申请日：2023-05-03

Applicant: Montage Technology Co., Ltd.

Inventor： Dongming LOU ,  Weidong FAN ,  Zhongyuan Chang

IPC: G01R31/319 ,  G01R31/28

CPC classification number: G01R31/31905 ,  G01R31/2879 ,  G01R31/31924 ,  G01R27/14

Abstract: A test circuit includes a signal processor, a first resistor, a second resistor, a first switch, and a second switch. The signal processor is coupled to a first drive end, a second drive end, a first sensing end, and a second sensing end. The first resistor is coupled between the first drive end and the first sensing end. The second resistor is coupled between the second drive end and the second sensing end. The first switch is coupled between the first sensing end and a first end of a device under test. The second switch is coupled between the second sensing end and a second end of the device under test. The first drive end is coupled to the first end of the device through a first transmission wire, and the second drive end is coupled to the second end of the device through a second transmission wire.

公开(公告)号：US20240337686A1

公开(公告)日：2024-10-10

申请号：US18478038

申请日：2023-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tanmay Neema ,  Kanak Das ,  Rajavelu Thinakaran ,  Gautam Nandi

IPC: G01R31/28 ,  H03F3/45 ,  H03M1/66

CPC classification number: G01R31/2879 ,  G01R31/2889 ,  H03F3/45475 ,  H03M1/662 ,  H03F2200/261

Abstract: The techniques and circuits, described herein, include solutions for error compensation in source measurement units (SMUs). An example SMU is capable of both sourcing current to a device under test (DUT) and measuring current through the DUT. An SMU may include a sensing resistor coupled in series with the DUT. A voltage across the sensing resistor may be measured by a current sensing amplifier in order to determine the output current through the DUT. In practice, the resistance of the sensing resistor may vary depending on manufacturing tolerances, etc. A gain of the current sensing amplifier may be calibrated in order to compensate for sensing resistor variance, which increases the accuracy with which current to the DUT can be sourced and measured.

公开(公告)号：US12007436B2

公开(公告)日：2024-06-11

申请号：US18363143

申请日：2023-08-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Tzu-Jin Yeh

IPC: G01R31/28

CPC classification number: G01R31/2884 ,  G01R31/2853 ,  G01R31/2879

Abstract: An IC includes a device-under-test (DUT) configured to receive a first AC signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal, and first and second detection circuits. Each of the first and second detection circuits includes a first gain stage coupled to a corresponding one of the first or second nodes through a first capacitive device, a second gain stage in a cascade arrangement with the first gain stage, and a low-pass filter configured to generate a DC signal based on an output signal of the second gain stage.

公开(公告)号：US11982707B2

公开(公告)日：2024-05-14

申请号：US17873385

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junsik Park ,  Heesu Kim ,  Bonggyu Kang ,  Youngmin Ku ,  Namsu Kim

IPC: G01R31/28 ,  G01R27/26 ,  H05K1/18

CPC classification number: G01R31/2884 ,  G01R27/2611 ,  G01R31/2879 ,  H05K1/181 ,  H05K2201/1003

Abstract: A semiconductor device includes an internal circuit connected to at least one pad. A first inductor element is connected between the at least one pad and the internal circuit, a second inductor element coupled to the first inductor element and generating an induced voltage due to an overcurrent flowing in the first inductor element. An event detection circuit includes a monitoring element connected to the second inductor element. The monitoring element is configured to generate an event detection signal by sensing changes in properties of the monitoring element caused by at least one of the induced voltages generated in the second inductor element and a current flowing in the second inductor element. The internal circuit supplies an operating voltage to the event detection circuit, and determines whether an event causing the overcurrent has occurred by receiving the event detection signal from the event detection circuit.

公开(公告)号：US11982701B2

公开(公告)日：2024-05-14

申请号：US17890233

申请日：2022-08-17

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Shuhei Tatemichi ,  Kenichi Ishii

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R31/261 ,  G01R31/2879 ,  H01L22/14

Abstract: Provided is a test method comprising: preparing a plurality of groups for setting, each of which has a plurality of semiconductor devices for setting, and assigning an inspection voltage to each of the respective plurality of groups for setting; performing first testing by applying the assigned inspection voltage to the semiconductor devices for setting, and testing, at a first temperature, the plurality of semiconductor devices for setting included in each of the plurality of groups for setting; performing second testing by testing, at a second temperature different from the first temperature, a semiconductor device for setting having been determined as being non-defective and by detecting a breakdown voltage at which the semiconductor device for setting is broken; acquiring a relationship between the inspection voltage and the breakdown voltage; and setting an applied voltage used when testing a semiconductor device under test at the first temperature, based on the acquired relationship.

公开(公告)号：US20240077530A1

公开(公告)日：2024-03-07

申请号：US18331596

申请日：2023-06-08

Applicant: Kioxia Corporation

Inventor： Tetsuharu KOJIMA

IPC: G01R31/28 ,  G01R1/04

CPC classification number: G01R31/2868 ,  G01R1/0458 ,  G01R31/2879

Abstract: According to a certain embodiment, a test board on which a device under test and a test executable integrated circuit configured to execute a test of the device under test are mounted, includes a first input/output terminal, a second input/output terminal, and a contact unit. The first input/output terminal connects a first measuring apparatus capable of supplying electric power to the test board and controlling the test executable integrated circuit. The second input/output terminal connects a second measuring apparatus capable of measuring electrical characteristics of the test executable integrated circuit. The contact unit is mounted on the test board through the second input/output terminal, and capable of electrically connecting the second measuring apparatus. There are provide the test board; and a diagnostic system, a diagnostic method, and a non-transitory computer-readable storage medium storing a diagnostic program, capable of diagnosing the test executable integrated circuit mounted on the test board.

公开(公告)号：US11892501B1

公开(公告)日：2024-02-06

申请号：US17865104

申请日：2022-07-14

Applicant: Cadence Design Systems, Inc.

Inventor： Arvind Chokhani ,  Joseph M. Swenton ,  Martin Amodeo

IPC: G01R31/28

CPC classification number: G01R31/287 ,  G01R31/2879 ,  G01R31/2882

Abstract: An integrated circuit (IC) test engine generates N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design. A diagnostics engine that receives test result data characterizing application of the N-cycle at-speed test patterns to a fabricated IC chip based on the IC design by an ATE, in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern. The diagnostics engine employs a fault simulator to fault-simulate the N-cycle at-speed test patterns against a fault model that includes a first set of transition faults and/or defects and fault-simulate a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting.

公开(公告)号：US11892499B2

公开(公告)日：2024-02-06

申请号：US17480369

申请日：2021-09-21

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kang Lv ,  Yang Xiong ,  Jian Hu

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2863 ,  G01R31/2642 ,  G01R31/2879

Abstract: Embodiments of the present application provide a testing equipment and a testing method. The testing equipment includes: a plurality of pad groups and a plurality of source measure units. Each of the pad groups has a stress pad. The stress pad is configured to connect an element under test. The source measure unit is configured to send an input signal to the element under test through the stress pad and measure an output signal of the element under test to acquire performance parameters of the element under test. The stress pads of at least two of the pad groups are connected to the corresponding source measure units at the same time. The embodiments of the present application help improve the testing efficiency.

公开(公告)号：US11860225B2

公开(公告)日：2024-01-02

申请号：US17678307

申请日：2022-02-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Fukumi Unokuchi ,  Toshitsugu Ishii

IPC: G01R31/28

CPC classification number: G01R31/2887 ,  G01R31/2879 ,  G01R31/2893 ,  G01R31/2896

Abstract: A test apparatus includes a test board, a unit, and a probe pin housed in the unit. First and second tip portions of the probe pin have the same shape as each other. A first external terminal of a first semiconductor package is brought into contact with the first tip portion of the probe pin and the second tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package. Then, the unit is turned upside down and rearranged in the test apparatus. Thereafter, a second external terminal of a second semiconductor package is brought into contact with the second tip portion of the probe pin and the first tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.

公开(公告)号：US20230366925A1

公开(公告)日：2023-11-16

申请号：US18359906

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JUN HE ,  YU-TING LIN ,  WEI-HSUN LIN ,  YUNG-LIANG KUO ,  YINLUNG LU

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2879 ,  G01R31/2642 ,  G01R31/2886

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.