-
公开(公告)号：US12184061B2
公开(公告)日：2024-12-31
申请号：US18071712
申请日：2022-11-30
Applicant: MONTAGE TECHNOLOGY CO., LTD.
Inventor： Xiong Zhang , Chunlai Sun
Abstract: An electrostatic discharge and electrical overstress detection circuit includes protection circuit, sensing circuit, clamp circuit, several stages of sampling logic circuits connected in sequence and storage circuit. Protection circuit is coupled between input/output pin and internal chip and discharges to a power supply terminal when the electrostatic discharge or electrical overstress events happen. Sensing circuit and clamp circuit are coupled between power supply terminal and ground terminal. Each stage of sampling logic circuit is coupled to power supply terminal and memory cell of storage circuit, and the first stage of sampling logic is coupled to the clamp circuit, and when the electrostatic discharge or electrical overstress events happen, the several stages of sampling logic circuits sample voltage of the power supply terminal one by one and change state of corresponding memory cell, so that the electrostatic discharge or electrical overstress events are successively recorded by the memory cell.
-
公开(公告)号：US20240273356A1
公开(公告)日：2024-08-15
申请号：US18433358
申请日：2024-02-05
Applicant: MONTAGE TECHNOLOGY CO., LTD.
IPC: G06N3/08
CPC classification number: G06N3/08
Abstract: A data processing method for a neural network implemented by a computing device and comprises a plurality of layers, the computing device comprises a first and a second memory, weight data of each of the plurality of layers is stored in the second memory, input data and output data have respective predetermined storage locations, the method comprises: performing batch processing to input data and weight data with a predetermined batch size; the predetermined batch size is determined using the following steps: determining actual storage locations of the input data and the output data of each layer when data is processed in batches using batch size candidates; determining memory access conditions of the second memory for each layer when data is processed in batches using batch size candidates; determining total memory access amount of the neural network corresponding to batch size candidates; selecting the predetermined batch size.
-
公开(公告)号：US11983118B2
公开(公告)日：2024-05-14
申请号：US17560204
申请日：2021-12-22
Applicant: MONTAGE TECHNOLOGY CO., LTD.
Inventor： Qiang Li , Yi Li , Liangliang Niu , Dongjie Tang , Yongjian Lv
IPC: G06F12/10
CPC classification number: G06F12/10
Abstract: The present disclosure provides a method and apparatus for parsing contiguous system addresses, and an electronic device. The method for parsing contiguous system addresses comprises: acquiring system level information upon receiving contiguous system addresses; acquiring logical address ranges of objects in a first level based on the contiguous system addresses and the system level information; and when successively acquiring logical address ranges of objects in a second level, . . . , or an Nth level of the system, acquiring logical address ranges of objects in a present level based on a logical address range of a previous level and the system level information, wherein N is the number of levels, and N is an integer greater than or equal to 2, and a logical address range of an object comprises a start address and an end address of the object.
-
公开(公告)号：US20240111690A1
公开(公告)日：2024-04-04
申请号：US18373381
申请日：2023-09-27
Applicant: MONTAGE TECHNOLOGY CO., LTD.
Inventor： Xiaoyan LI , Zhaohui DU , Men LONG , Yang CHAO , Dajiang ZHONG , Zhixin TIAN
CPC classification number: G06F12/1408 , G06F7/584 , G06F12/1441
Abstract: This application relates to the field of memory technology, in particular to a method and a system for remapping a row address on a multichannel DIMM. The method is applied to a memory controller, comprising: receiving a first read/write access address and extracting a first channel row address from the first read/write access address; encrypting and mapping the first channel row address through a key-based mapping method to obtain a second channel row address that corresponds to the first channel row address within a predetermined address range; forming a second read/write access address based on the second channel row address and unextracted address information in the first read/write access address, and performing read/write access to the DIMM based on the second read/write access address. The present application can alleviate side channel attack without causing degradation of read/write performance.
-
公开(公告)号：US11855631B2
公开(公告)日：2023-12-26
申请号：US17406370
申请日：2021-08-19
Applicant: MONTAGE TECHNOLOGY CO., LTD.
Inventor： Xiong Zhang , Chunlai Sun , Juan Du , Gang Shi , Chonghe Yang
IPC: H03K19/0944 , H03K19/003 , H03K17/10 , H03K17/687 , H03K19/00
CPC classification number: H03K19/0944 , H03K17/102 , H03K17/687 , H03K19/0005 , H03K19/00315
Abstract: An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.
-
Patent Agency Ranking
6.发明公开公开(公告)号：US20230342205A1
公开(公告)日：2023-10-26
申请号：US18129098
申请日：2023-03-31
Applicant: MONTAGE TECHNOLOGY CO., LTD.
Inventor： Yu CAI
CPC classification number: G06F9/5027 , G06F9/547
Abstract: A multi-processing accelerating method and a multi-processing accelerating system based on an electronic-system-level virtual platform are provided. The method includes: creating a controller domain and a plurality of client domains on the electronic-system-level virtual platform, each client domain corresponds to a process; and controlling, by the controller domain, the client domains in parallel to enable multi-processing for the client domains. The multi-processing accelerating method and the system for the electronic-system-level virtual platform can effectively accelerate the operation of the electronic-system-level virtual platform and improve the efficiency of software development of the electronic-system-level virtual platform.
-
公开(公告)号：US20220399247A1
公开(公告)日：2022-12-15
申请号：US17836351
申请日：2022-06-09
Applicant: MONTAGE TECHNOLOGY CO., LTD.
Inventor： Xiong ZHANG
IPC: H01L23/38
Abstract: On-chip peltier cooling devices and manufacturing methods thereof are provided. The device comprises: a first type well, a polysilicon gate and dummy gates, first type doped regions, a second type doped region, a first and second via. The dummy gate is formed as a two-segment structure with an interval, and there is no gate oxide layer between portions of the dummy gate which are far away from the interval and the semiconductor substrate. The first type doped region at least overlaps with an orthographic projection region of the first segment of the dummy gate on the semiconductor substrate. The second type doped region at least overlaps with orthographic projection regions of the polysilicon gate and the second segment of the dummy gate on the semiconductor substrate. In this application, the heat flows from inside of the device to its surface, to realize heat dissipation and cooling.
-
公开(公告)号：US20220344930A1
公开(公告)日：2022-10-27
申请号：US17458608
申请日：2021-08-27
Applicant: MONTAGE TECHNOLOGY CO., LTD.
Inventor： Chunlai SUN
Abstract: The present disclosure provides a power clamp circuit, a chip, and a dual-clamp method. The power clamp circuit is applied to a circuit system to monitor the power supply voltage of the circuit system and includes: an EOS protection module, for outputting an EOS protection triggering signal when it is determined that the circuit system is electrically overstressed based on the power supply voltage; an ESD protection module, for outputting an ESD protection triggering signal when it is determined that an electrostatic event is present in the circuit system based on the power supply voltage; a switch control module, for turning on a discharge path based on the EOS protection signal to discharge an EOS current, and turning on the discharge path based on the ESD protection signal to discharge an electrostatic current.
-
公开(公告)号：US20220164671A1
公开(公告)日：2022-05-26
申请号：US17533082
申请日：2021-11-22
Applicant: MONTAGE TECHNOLOGY CO., LTD.
Inventor： Zhen DONG , Yuanfei NIE , Huan FENG
IPC: G06N3/08
Abstract: A method for compressing a neural network includes: obtaining a neural network including a plurality of parameters to be compressed; dividing the parameters into J blocks; compressing a jth block with Kj compression ratios to generate Kj operation branches; obtaining Kj weighting factors; replacing the jth block with the Kj operation branches weighted by the Kj weighting factors to generate a replacement neural network; performing forward propagation to the replacement neural network, a weighted sum operation being performed on Kj operation results generated by the Kj operation branches with the Kj weighting factors and a result of the operation being used as an output; performing backward propagation to the replacement neural network, updated values of the Kj weighting factors being calculated based on a model loss; and determining an operation branch corresponding to the maximum value of the updated values of the Kj weighting factors as a compressed jth block.
-
公开(公告)号：US20220060187A1
公开(公告)日：2022-02-24
申请号：US17406370
申请日：2021-08-19
Applicant: MONTAGE TECHNOLOGY CO., LTD.
Inventor： Xiong ZHANG , Chunlai SUN , Juan DU , Gang SHI , Chonghe YANG
IPC: H03K19/0944 , H03K19/003 , H03K19/00 , H03K17/687 , H03K17/10
Abstract: An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.
-
-
-
-
-
-
-
-
-
Search Results
92
records
(took 0.023 seconds)
