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1305 条记录 (耗时 0.035 秒)

    POWER MOSFET DRIVING CIRCUIT WITH TRANSFER CURVE GATE DRIVER AND GROUND SHIFT COMPENSATION
    2.
    发明公开
    POWER MOSFET DRIVING CIRCUIT WITH TRANSFER CURVE GATE DRIVER AND GROUND SHIFT COMPENSATION 审中-公开

    公开(公告)号：US20240348248A1

    公开(公告)日：2024-10-17

    申请号：US18235507

    申请日：2023-08-18

    申请人： Curtis Instruments, Inc.

    发明人： Boripann Srivongse

    IPC分类号： H03K17/687 ,  H03K17/10 ,  H03K17/16

    CPC分类号： H03K17/6871 ,  H03K17/102 ,  H03K17/162

    摘要： A waveshape circuit for a motor includes at least a first transistor, a second transistor, a first subcircuit, and a second subcircuit. The first transistor is configured to, during turn on, substantially pass a current through the waveshape circuit and block the current, during turn off, for a transition of a power circuit of the motor. The second transistor is configured to, during turn on, substantially block the current through the waveshape circuit and substantially pass current, during turn off, for the transition for the power circuit of the motor according to a transfer function. The first subcircuit is coupled to the first transistor and configured to determine a first slope region of the transfer function for the waveshape circuit. The second subcircuit is coupled to the first transistor and configured to determine a second slope region of the transfer function for the waveshape circuit.

    SWITCH WITH CASCODE ARRANGEMENT
    3.
    发明公开
    SWITCH WITH CASCODE ARRANGEMENT 审中-公开

    公开(公告)号：US20240340011A1

    公开(公告)日：2024-10-10

    申请号：US18295498

    申请日：2023-04-04

    申请人： NXP USA, Inc.

    发明人： David Edward Bien ,  Xu Jason Ma

    IPC分类号： H03K19/0185 ,  H03K17/10 ,  H03K17/687

    CPC分类号： H03K19/018528 ,  H03K17/102 ,  H03K17/6872

    摘要： A switching device may include an input terminal, an output terminal, a primary switching transistor coupled between the input terminal and the output terminal, logic circuitry configured to receive a control signal to selectively activate the switching device, a first cascode arrangement coupled between the logic circuitry and a first reference voltage supply, and a second cascode arrangement coupled between the input terminal and the primary switching transistor. The first cascode arrangement may include cascode transistors having gate terminals coupled to a first voltage divider coupled between the first reference voltage supply and a second reference voltage supply that is coupled to the logic circuitry. The second cascode arrangement may include a first cascode transistor coupled to a fixed voltage at the first voltage divider and second and third cascode transistors coupled to variable cascode bias voltages at a second voltage divider coupled to a variable voltage input.

    CLAMP CIRCUITS
    4.
    发明公开
    CLAMP CIRCUITS 审中-公开

    公开(公告)号：US20240340001A1

    公开(公告)日：2024-10-10

    申请号：US18610589

    申请日：2024-03-20

    申请人： Infineon Technologies AG

    发明人： Dieter Draxelmayr ,  Herwig Wappis

    IPC分类号： H03K17/30 ,  H03K17/081 ,  H03K17/10

    CPC分类号： H03K17/302 ,  H03K17/08104 ,  H03K17/102

    摘要： A clamp circuit including a first transistor having a control connection coupled to a first reference voltage terminal and a first controlled connection coupled to an input voltage terminal. The clamp circuit includes a second transistor having a control connection configured to receive a control voltage that is dependent on a current flowing through the first transistor, a first controlled connection coupled to the input voltage terminal, and a second controlled connection coupled to a second reference voltage terminal.

    LOW VOLTAGE DETECTION FLOATING N WELL BIAS CIRCUIT
    8.
    发明公开
    LOW VOLTAGE DETECTION FLOATING N WELL BIAS CIRCUIT 审中-公开

    公开(公告)号：US20240267043A1

    公开(公告)日：2024-08-08

    申请号：US18316291

    申请日：2023-05-12

    申请人： DB HiTek Co., Ltd.

    发明人： Sang Mok LEE ,  Hyun Sup JUNG ,  Seung Hyun KOU

    IPC分类号： H03K17/16 ,  H03K17/10 ,  H03K17/687

    CPC分类号： H03K17/162 ,  H03K17/102 ,  H03K17/687

    摘要： Disclosed is a low-voltage detection floating N-well bias circuit. The circuit includes a power detector configured to detect states of first power (VDD) and second power (DVDD) at different power levels; a switch configured to perform a switching operation according to the states of the first power (VDD) and the second power (DVDD); and a voltage output circuit configured to output the first power (VDD) or the second power (DVDD) as an N-well bias voltage according to the states of the first power (VDD) and the second power (DVDD) and the switching operation of the switch. Accordingly, when the first power (VDD) and the second power (DVDD) are supplied and the second power (DVDD) has a low voltage state, the floating N-well bias circuit can continuously bias an N-well with the second power (DVDD), without dropping the second power (DVDD).