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公开(公告)号：US20240340001A1
公开(公告)日：2024-10-10
申请号：US18610589
申请日：2024-03-20
发明人： Dieter Draxelmayr , Herwig Wappis
IPC分类号： H03K17/30 , H03K17/081 , H03K17/10
CPC分类号： H03K17/302 , H03K17/08104 , H03K17/102
摘要： A clamp circuit including a first transistor having a control connection coupled to a first reference voltage terminal and a first controlled connection coupled to an input voltage terminal. The clamp circuit includes a second transistor having a control connection configured to receive a control voltage that is dependent on a current flowing through the first transistor, a first controlled connection coupled to the input voltage terminal, and a second controlled connection coupled to a second reference voltage terminal.
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公开(公告)号：US20200145016A1
公开(公告)日：2020-05-07
申请号：US16672706
申请日：2019-11-04
发明人： Dieter Draxelmayr
IPC分类号： H03M1/06
摘要： A circuit arrangement includes charge stores logically arranged in an array configuration having logical columns of charge stores including at least first, second, third and fourth columns of charge stores. A control circuit is configured to control a switching network operably coupled to the charge stores, and to affect a first circuit configuration in a first time segment and a second circuit configuration in a second time segment, the circuit configurations being different from one another. In the first circuit configuration, the first and third columns of charge stores receive a first polarity component of a differential signal, and the second and fourth columns of charge stores receive a second polarity component of the differential signal. In the second circuit configuration, the first and second columns of charge stores receive the first polarity component, and the third and fourth columns of charge stores receive the second polarity component.
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公开(公告)号：US08872589B2
公开(公告)日：2014-10-28
申请号：US13623583
申请日：2012-09-20
IPC分类号： H03G3/12
CPC分类号： H03F3/005 , H03F3/45475 , H03F2200/411 , H03F2203/45512 , H03F2203/45544 , H03F2203/45561 , H03G1/0094
摘要： In accordance with an embodiment, a system includes a programmable gain amplifier having a switchable feedback capacitor coupled in parallel with a first capacitor and a controller. The controller is configured to couple the feedback capacitor between an input node of the programmable gain amplifier and an output node of the programmable gain amplifier in a first gain setting, and switch a first terminal of the feedback capacitor from the output of the programmable gain amplifier to a reference node while a second terminal of the feedback capacitor remains coupled to the input node of the programmable gain amplifier for a first time period when transitioning from the first gain setting to a second gain setting.
摘要翻译： 根据实施例，系统包括可编程增益放大器，其具有与第一电容器和控制器并联耦合的可切换反馈电容器。 控制器被配置为在第一增益设置中将可编程增益放大器的输入节点和可编程增益放大器的输出节点之间的反馈电容器耦合，并且从可编程增益放大器的输出端切换反馈电容器的第一端子 到反馈电容器的第二端子在从第一增益设置转换到第二增益设置的第一时间段期间保持耦合到可编程增益放大器的输入节点。
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公开(公告)号：US09213350B2
公开(公告)日：2015-12-15
申请号：US13970570
申请日：2013-08-19
发明人： Dieter Draxelmayr
CPC分类号： G05F3/24 , G05F3/262 , H03F1/56 , H03F2200/222
摘要： In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.
摘要翻译： 在一个实现中，装置可以包括耦合到第一电压源的第一负沟道金属氧化物半导体（NMOS）晶体管电路，耦合到第一电压源的第二NMOS晶体管电路，第二NMOS晶体管电路具有较小的沟道宽度 沟道长度比，第一正沟道金属氧化物半导体（PMOS）晶体管电路耦合到第二电压源并耦合到第二NMOS晶体管电路;以及第二PMOS晶体管，耦合到第二电压源， 第二PMOS晶体管电路具有比第一PMOS晶体管电路更大的沟道宽度与沟道长度比。
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5.发明申请Apparatus and a Method for Generating a Sensor Signal Indicating Information on a Capacitance of a Variable Capacitor Comprising a Variable Capacitance 审中-公开用于产生传感器信号的装置和方法，其指示包含可变电容的可变电容器的电容的信息公开(公告)号：US20140266260A1
公开(公告)日：2014-09-18
申请号：US13835274
申请日：2013-03-15
IPC分类号： G01R27/26
CPC分类号： G01R27/2605 , G01D5/241 , H04R19/005 , H04R19/04
摘要： An apparatus for generating a sensor signal indicating information on a capacitance of a variable capacitor including a variable capacitance includes a sensor unit and a compensation unit. The sensor unit is configured to generate a sensor signal indicating information on a varying current flowing through a connection between the sensor unit and the variable capacitor caused by a variation of the capacitance of the variable capacitor while the variable capacitor is biased by a predefined bias voltage. Further, the compensation unit is configured to influence the sensor signal or to provide a compensation signal capable of influencing the sensor signal so that the sensor signal includes less nonlinear signal portions than a sensor signal without the influence of the compensation unit or the compensation signal.
摘要翻译： 一种用于产生指示包括可变电容的可变电容器的电容的信息的传感器信号的装置包括传感器单元和补偿单元。 所述传感器单元被配置为产生传感器信号，所述传感器信号指示流过所述传感器单元和所述可变电容器之间的连接的变化电流的信息，所述变化电流由所述可变电容器的电容的变化引起，同时所述可变电容器被偏置预定的偏置电压 。 此外，补偿单元被配置为影响传感器信号或提供能够影响传感器信号的补偿信号，使得传感器信号包括比传感器信号更少的非线性信号部分，而不受补偿单元或补偿信号的影响。
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公开(公告)号：US11196437B1
公开(公告)日：2021-12-07
申请号：US17108624
申请日：2020-12-01
发明人： Dieter Draxelmayr
IPC分类号： H03M1/10
摘要： In accordance with an embodiment, a method for operating an analog-to-digital converter (ADC) includes: determining a trip point of a comparator of the ADC by applying a first signal having a first slope to an input of the ADC, and monitoring an output state of the comparator in response to the first signal; and after applying the first signal, applying a second signal having a second signal level based on the determined trip point of the comparator, monitoring values of an output code of the ADC in response to the second signal, and generating statistical information based on the monitored values of the output code, where the second signal is a static signal or has as second slope less than the first slope.
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公开(公告)号：US09912341B2
公开(公告)日：2018-03-06
申请号：US13783054
申请日：2013-03-01
发明人： Dieter Draxelmayr
CPC分类号： H03M1/0692 , H03M1/00 , H03M1/12 , H03M1/468 , H03M1/804
摘要： Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient ADC. For example, a successive approximation capacitor arrangement may include multiple arrays with non-binary bit weights.
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公开(公告)号：US08994411B2
公开(公告)日：2015-03-31
申请号：US14053369
申请日：2013-10-14
发明人： Dieter Draxelmayr , Karl Norling
CPC分类号： H03K17/94 , H02M3/337 , H02M7/538 , H03K5/1515 , H03K2017/6875 , H03K2217/0081
摘要： In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.
摘要翻译： 根据实施例，驱动器电路包括低侧驱动器，其具有被配置为耦合到第一半导体开关的控制节点的第一输出和被配置为耦合到第一半导体开关的参考节点的参考输入 。 低侧驱动器还包括耦合在第一半导体开关的输出节点和第一节点之间的第一电容器，耦合在第一节点和驱动器的第一电源输入端之间的第一二极管以及耦合在第一节点之间的第二电容器 低侧驱动器和第一半导体开关的参考节点的功率输入。
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公开(公告)号：US08754675B2
公开(公告)日：2014-06-17
申请号：US13934980
申请日：2013-07-03
发明人： Dieter Draxelmayr , Karl Norling
IPC分类号： H03K3/00
CPC分类号： H02M1/08 , H02M3/33553 , H03K17/063 , H03K17/691
摘要： In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.
摘要翻译： 根据实施例，用于驱动开关的电路包括驱动器电路。 驱动器电路包括被配置为耦合到JFET的栅极的第一输出，被配置为耦合到MOSFET的栅极的第二输出，第一电源节点和被配置为耦合到公共节点的偏置输入 。 待驱动的开关包括耦合到公共节点处的MOSFET的JFET。
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公开(公告)号：US10784879B2
公开(公告)日：2020-09-22
申请号：US16672706
申请日：2019-11-04
发明人： Dieter Draxelmayr
IPC分类号： H03M1/06
摘要： A circuit arrangement includes charge stores logically arranged in an array configuration having logical columns of charge stores including at least first, second, third and fourth columns of charge stores. A control circuit is configured to control a switching network operably coupled to the charge stores, and to affect a first circuit configuration in a first time segment and a second circuit configuration in a second time segment, the circuit configurations being different from one another. In the first circuit configuration, the first and third columns of charge stores receive a first polarity component of a differential signal, and the second and fourth columns of charge stores receive a second polarity component of the differential signal. In the second circuit configuration, the first and second columns of charge stores receive the first polarity component, and the third and fourth columns of charge stores receive the second polarity component.
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