-
1.发明授权公开(公告)号：US12125841B2
公开(公告)日：2024-10-22
申请号：US17877001
申请日：2022-07-29
IPC分类号： H01L27/02
CPC分类号： H01L27/0248
摘要： A semiconductor device includes a semiconductor body including an upper surface, input and output terminals disposed on the upper surface of the semiconductor body, first and second p-n junction devices that are monolithically integrated in the semiconductor body, and a signal line protection circuit connected between the input and output terminals and comprising a low-pass filter and a voltage clamping device, wherein each of the low-pass filter and the voltage clamping device include the first and second p-n junction devices.
-
公开(公告)号：US20240348244A1
公开(公告)日：2024-10-17
申请号：US18634554
申请日：2024-04-12
IPC分类号： H03K17/10 , H03K17/0412 , H03K17/30
CPC分类号： H03K17/102 , H03K17/04123 , H03K17/302
摘要： In accordance with an embodiment, a method includes: operating a driver circuit in an idle mode in which portion of the driver circuit are deactivated, wherein the driver circuit is coupled to a first transistor and a second transistor coupled between a supply node and a first circuit node configured to be connected to a load, and operating the driver circuit in the idle mode comprises the driver circuit switching off the first transistor, switching on the second transistor; detecting a change in a voltage across the first transistor; and in response to the change in voltage being detected, activating the inactive portions of the driver circuit to switch on the first transistor and leave the idle mode.
-
3.发明公开公开(公告)号：US20240347788A1
公开(公告)日：2024-10-17
申请号：US18298941
申请日：2023-04-11
CPC分类号： H01M10/425 , H01M10/441 , H02J7/0019 , H02J7/00714 , H01M2010/4271
摘要： In some examples, this disclosure describes a method of operating a plurality of battery management circuits of a battery management system associated with an electric device. The method may comprise adjusting a first trim value associated with a first battery management circuit during operation of the electric device, and adjusting a second trim value associated with a second battery management circuit during operation of the electric device. The method may also comprise sinking a first amount of current in the first battery management circuit based on the first trim value; and sinking a second amount of current in the second battery management circuit based on the second trim value, wherein sinking the first amount of current and sinking the second amount of current causes the first battery management circuit and the second battery management circuit to consume substantially similar amounts of current.
-
公开(公告)号：US20240339995A1
公开(公告)日：2024-10-10
申请号：US18605449
申请日：2024-03-14
IPC分类号： H03K5/02 , H03K17/687
CPC分类号： H03K5/02 , H03K17/6871
摘要： The present disclosure provides a capacitance circuit which has an input terminal and is configured to provide an increased capacitance between the input terminal and a first reference voltage. The capacitance circuit comprises a current source structure configured to provide a compensation current at the input terminal, a first transistor having a first control terminal and a first load current and being coupled to the input terminal, a second transistor having a second control terminal, a capacitance amplification circuit configured to provide a capacitance amplification factor and being coupled between the first control terminal and the second control terminal, and a capacitor having a core capacitance and being coupled between the first control terminal and the input terminal, wherein the compensation current corresponds to the first load current during direct current operation, and wherein the increased capacitance is based on the core capacitance and the capacitance amplification factor.
-
公开(公告)号：US20240339416A1
公开(公告)日：2024-10-10
申请号：US18130692
申请日：2023-04-04
IPC分类号： H01L23/544 , H01L23/495 , H01L23/498
CPC分类号： H01L23/544 , H01L23/49541 , H01L23/49838 , H01L2223/54413
摘要： Substrates for use with semiconductor devices are provided. The substrates include a barcode laser etched into a metallic surface or layer of the substrate. A wall of non-metallic material may be formed on the metallic surface or layer and frame the barcode. Separately or in combination, an optically transparent encapsulant may cover a region of the metallic surface or layer that includes the barcode, where the optically transparent encapsulant reduces oxidation of metallic debris produced by laser etching of the barcode and that remains on or near the barcode. Separately or in combination, the substrate may include an electrically insulative body covered by the metallic layer and a trench formed in the metallic layer along a perimeter of the barcode and that exposes the electrically insulative body. Methods of improving readability of the barcode are also provided.
-
公开(公告)号：US12112992B2
公开(公告)日：2024-10-08
申请号：US18107800
申请日：2023-02-09
发明人： Daniel Porwol , Thomas Fischer , Uwe Seidel , Anton Steltenpohl
IPC分类号： H01L23/31 , H01L21/683 , H01L23/29 , H01L23/00
CPC分类号： H01L23/3164 , H01L23/3121 , H01L23/3135 , H01L23/3192 , H01L21/6836 , H01L23/295 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/32 , H01L2221/68327 , H01L2221/68368 , H01L2224/02377 , H01L2224/02381 , H01L2224/05569 , H01L2224/13024 , H01L2224/16225 , H01L2224/32225 , H01L2924/10252 , H01L2924/10253 , H01L2924/10254 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/10335
摘要： A package includes: an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and an encapsulant encapsulating the dielectric layer and the semiconductor die. The encapsulant is a mold compound having different material properties than the dielectric layer. A method of manufacturing package is also described.
-
公开(公告)号：US12109645B2
公开(公告)日：2024-10-08
申请号：US18235428
申请日：2023-08-18
IPC分类号： B23K20/00 , B23K20/10 , B23K101/36 , B23K103/12
CPC分类号： B23K20/106 , B23K2101/36 , B23K2103/12
摘要： A method of welding includes providing first and second joining partners, providing a welding apparatus that includes a sonotrode comprising a structured working surface, arranging the first and second joining partners to contact one another, and forming a welded connection between the first and second joining partners by contacting the first joining partner with the structured working surface and vibrating the sonotrode at an ultrasonic frequency, wherein the structured working surface comprises a plurality of apexes, a plurality of nadirs between immediately adjacent ones of the apexes, and planar sidewalls that extend between the nadirs and the apexes, and wherein for each of the apexes the planar sidewalls on either side of the respective apex extend along first and second planes that intersect one another at an acute angle.
-
8.发明公开公开(公告)号：US20240332136A1
公开(公告)日：2024-10-03
申请号：US18609133
申请日：2024-03-19
IPC分类号： H01L23/495
CPC分类号： H01L23/49537 , H01L23/49548 , H01L23/49575
摘要： A power semiconductor device includes: at least one substrate; at least one power semiconductor die arranged over the at least one substrate; a first leadframe arranged over the at least one power semiconductor substrate and over the at least one power semiconductor die, the first leadframe being arranged at least partially in a first plane and including one or more connecting portions extending out of the first plane in a first direction; and a second leadframe at least partially arranged in a second plane above or below the first plane and including one or more attachment sites. The one or more connecting portions extend into the second plane at the one or more attachment sites. The one or more connecting portions are arranged at a non-zero distance from the second leadframe, the non-zero distance being bridged by weld seams at the one or more attachment sites.
-
公开(公告)号：US20240329166A1
公开(公告)日：2024-10-03
申请号：US18194749
申请日：2023-04-03
发明人： Bernhard ENDRES , Jürgen FÖRSTER , Andreas STRAßER
CPC分类号： G01R33/093 , G01R33/091 , H10N50/10
摘要： A magnetoresistive sensor includes a sensing element and a stress inducing layer. The sensing element has a layer stack that includes a reference layer having a fixed reference magnetization aligned with a magnetization axis; a magnetic free layer having a magnetically free magnetization, wherein the magnetically free magnetization is variable in a presence of an external magnetic field; and a non-magnetic layer arranged between the reference layer and the magnetic free layer. The stress inducing layer is coupled to the layer stack and is configured to apply a force to the layer stack to induce a mechanical stress in the layer stack along a mechanical stress axis such that the magnetization axis is aligned parallel with the mechanical stress axis or perpendicular with the mechanical stress axis.
-
公开(公告)号：US12107026B2
公开(公告)日：2024-10-01
申请号：US17542905
申请日：2021-12-06
发明人： Raphael Hellwig , Philip Amos , Walter Hartner
IPC分类号： H01L23/34 , H01L23/498 , H01L23/552
CPC分类号： H01L23/34 , H01L23/49816 , H01L23/49822 , H01L23/552
摘要： A circuit arrangement has a chip arrangement in the form of an embedded Wafer Level Ball Grid Array (eWLB) arrangement with solder contacts on one side and a thermal interface on a side of the chip arrangement facing away from the solder contacts which is designed to dissipate heat from the semiconductor chip. In examples, the thermal interface has a thermally and electrically conductive material, wherein in a top view of the chip arrangement, a contact area in which the thermally and electrically conductive material is in thermal contact with the chip arrangement is limited to the fan-out area. In examples, the thermal interface has at least one RF absorption layer which is designed to absorb electromagnetic radiation at an operating frequency of the semiconductor chip.
-
-
-
-
-
-
-
-
-
搜索结果
11455 条记录 (耗时 0.041 秒)
