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公开(公告)号：US11387814B2
公开(公告)日：2022-07-12
申请号：US17008466
申请日：2020-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Aniruddha Roy , Nitin Agarwal , Rajavelu Thinakaran
Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.
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公开(公告)号：US10317925B2
公开(公告)日：2019-06-11
申请号：US15473209
申请日：2017-03-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Rajavelu Thinakaran , Sumit Dubey
Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.
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公开(公告)号：US20240337682A1
公开(公告)日：2024-10-10
申请号：US18478850
申请日：2023-09-29
Applicant: Texas Instruments Incorporated
Inventor： Rajavelu Thinakaran
IPC: G01R31/28 , H03K17/687
CPC classification number: G01R31/2834 , H03K17/6871
Abstract: In described examples, a system includes a resistor, a capacitor coupled to the resistor to form an RC circuit, and a charging circuit. The charging circuit is coupled to the resistor and to the capacitor. The charging circuit is configured to determine a voltage across the resistor, and to provide a current to the capacitor to increase a rate of charging or discharging of the capacitor. A magnitude and a polarity of the current are responsive to the voltage across the resistor. In some examples, the RC circuit is configured to compensate for a load capacitance of a parametric measurement unit, a source measurement unit, or a device power supply that is part of an automatic test equipment.
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公开(公告)号：US20240310411A1
公开(公告)日：2024-09-19
申请号：US18605556
申请日：2024-03-14
Applicant: Texas Instruments Incorporated
Inventor： Rajavelu Thinakaran , Gautam Salil Nandi , Hariharan Srinivasan , Rahul Shaw , Abhishek Ghosh , Taras Dudar
IPC: G01R1/067
CPC classification number: G01R1/06766
Abstract: An apparatus includes a circuit including a force amplifier having an output, a resistor having a first terminal coupled to the output of the force amplifier, and a second terminal. The circuit also includes a diode clamp including a first diode having a first terminal coupled to the first terminal of the resistor, and having a second terminal coupled to the second terminal of the resistor, the first diode having a first orientation. The diode clamp also includes a second diode coupled in parallel with the first diode between the first and second terminals of the resistor, the second diode having a second orientation opposite than the first diode.
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公开(公告)号：US11038517B1
公开(公告)日：2021-06-15
申请号：US16744614
申请日：2020-01-16
Applicant: Texas Instruments Incorporated
Inventor： Rajavelu Thinakaran
Abstract: A system includes a multiplying digital-to-analog converter (MDAC). The system also includes an input-side component coupled to the MDAC and configured to provide a code to the MDAC. The system also includes a reference voltage source coupled to the MDAC and configured to provide a reference voltage to the MDAC. The MDAC comprises a nonlinear calibration circuit configured to adjust an output of the MDAC nonlinearly based on the code, the reference voltage, and an output of the nonlinear calibration circuit.
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公开(公告)号：US08766700B1
公开(公告)日：2014-07-01
申请号：US14197320
申请日：2014-03-05
Applicant: Texas Instruments Incorporated
Inventor： Vineet Mishra , Rajavelu Thinakaran
IPC: H03K17/16
CPC classification number: H03K17/6871 , H03K17/04123 , H03K17/102 , H03K2217/0009 , H03K2217/0054
Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.
Abstract translation: 采样的CMOS开关包括在输入和输出节点之间串联的第一和第二NMOS器件。 第一和第二NMOS器件由采样信号激活。 一对低电压DEPMOS器件以“T”配置连接在输入和输出节点之间。 低电压DEPMOS器件由反向采样信号激活。 反馈电路包括DEPMOS器件以及第三高电压NMOS器件和电流源。 第三NMOS器件由输入节点上的信号控制。 开关根据反相采样信号的相位可切换地将模拟电压源连接到第三NMOS器件的源极和DEPMOS器件的栅极。 采样CMOS开关的结构使得能够保护低压DEPMOS晶体管的栅极氧化物绝缘体免受高压损坏。
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公开(公告)号：US09866237B1
公开(公告)日：2018-01-09
申请号：US15593618
申请日：2017-05-12
Applicant: Texas Instruments Incorporated
Inventor： Rajavelu Thinakaran , Sumit Dubey
CPC classification number: H03M3/422 , H03H19/004 , H03M1/1245 , H03M3/45
Abstract: Disclosed examples include switched capacitor integrator circuits including an amplifier, a feedback capacitor, a sampling capacitor, a loading capacitor and a switching circuit, along with a controller that operates the switching circuit to sample an input signal to the sampling capacitor during a sample portion of a given sample and hold cycle, to couple the sampling capacitor to an amplifier input during a first hold portion of each sample and hold cycle, and to couple the sampling capacitor and the loading capacitor to the amplifier input in a second hold portion of each sample and hold cycle to reduce the bandwidth and power consumption by the integrator circuit.
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公开(公告)号：US09252792B2
公开(公告)日：2016-02-02
申请号：US14275861
申请日：2014-05-12
Applicant: Texas Instruments Incorporated
Inventor： Rajavelu Thinakaran
CPC classification number: H03L7/0991 , H03K3/0315 , H03L7/02 , H03L7/06 , H03L7/099 , H03L7/105 , H03L2207/00
Abstract: A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a frequency-to-voltage (F2V) converter. The F2V converter, for example, includes a frequency target control input for selecting an operational frequency and in response generates a frequency control signal using a DAC (digital-to-analog converter). The example F2V converter is arranged using a split capacitor DAC to provide a linear voltage response over a range of trim codes. The clock generator is arranged to generate the converter clock signal in response to the frequency control signal.
Abstract translation: 例如，可调谐DCO（数字控制振荡器）包括时钟发生器，其被配置为提供用于驱动频率 - 电压（F2V）转换器的转换器时钟信号。 F2V转换器例如包括用于选择工作频率的频率目标控制输入，并且响应于使用DAC（数模转换器）产生频率控制信号。 示例F2V转换器使用分离电容DAC来布置，以在一系列修剪代码上提供线性电压响应。 时钟发生器被布置成响应于频率控制信号而产生转换器时钟信号。
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公开(公告)号：US08698546B1
公开(公告)日：2014-04-15
申请号：US13625609
申请日：2012-09-24
Applicant: Texas Instruments Incorporated
Inventor： Vineet Mishra , Rajavelu Thinakaran
IPC: H03K17/16
CPC classification number: H03K17/6871 , H03K17/04123 , H03K17/102 , H03K2217/0009 , H03K2217/0054
Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.
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公开(公告)号：US20240319260A1
公开(公告)日：2024-09-26
申请号：US18478825
申请日：2023-09-29
Applicant: Texas Instruments Incorporated
Inventor： Tanmay Neema , Rajavelu Thinakaran , Gautam Salil Nandi , Vishal Monteiro , Deepak Kumar Meher
IPC: G01R31/28
CPC classification number: G01R31/2834 , G01R31/2889
Abstract: In described examples, a test control circuit includes a subsystem and a transition control circuit. The subsystem outputs test signals to, and receives and measures response signals of, a device under test (DUT). The transition control circuit operates the test control circuit in response to a first operational state information indicating a first mode and a first set of configuration settings; receives a Transition Trigger signal and a second operational state information indicating a second mode and a second set of configuration settings; and, by performing allowed mode changes and in response to receiving the Transition Trigger signal, transitions the test control circuit to operating in response to the second operational state information. Allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode.
