公开(公告)号：US09966330B2

公开(公告)日：2018-05-08

申请号：US13829623

申请日：2013-03-14

申请人： VISHAY-SILICONIX

发明人： Kyle Terrill ,  Frank Kuo ,  Sen Mao

IPC分类号： H01L23/051 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/49575 ,  H01L21/561 ,  H01L23/051 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. The gate and source are flip chip coupled to the lead frame. The stack die package can include a second die including a gate and a drain that are located on a first surface of the second die and a source that is located on a second surface of the second die that is opposite the first surface. The source of the second die is facing the drain of the first die.

公开(公告)号：US09589929B2

公开(公告)日：2017-03-07

申请号：US13830041

申请日：2013-03-14

申请人： VISHAY-SILICONIX

发明人： Kyle Terrill ,  Frank Kuo ,  Sen Mao

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/544 ,  H01L23/31

CPC分类号： H01L25/074 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54486 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/41052 ,  H01L2224/411 ,  H01L2224/41105 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49105 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/8391 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/8491 ,  H01L2224/9221 ,  H01L2224/92246 ,  H01L2224/92252 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599

摘要： In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

摘要翻译： 在一个实施例中，一种方法可以包括将第一管芯的栅极和源极耦合到引线框架。 第一管芯可以包括位于第一管芯的第一表面上的栅极和源极，以及位于第一管芯的与第一表面相对的第二表面上的漏极。 此外，该方法可以包括将第二管芯的源耦合到第一管芯的漏极。 第二管芯可以包括位于第二管芯的第一表面上的栅极和漏极，以及位于第二管芯的与第一表面相对的第二表面上的源极。

公开(公告)号：US20170271304A1

公开(公告)日：2017-09-21

申请号：US15457790

申请日：2017-03-13

申请人： VISHAY-SILICONIX

发明人： Frank Kuo ,  Suresh Belani

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

摘要： A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

公开(公告)号：US20150331438A1

公开(公告)日：2015-11-19

申请号：US14811579

申请日：2015-07-28

申请人： VISHAY-SILICONIX

发明人： King Owyang ,  Mohammed Kasem ,  Yuming Bai ,  Frank Kuo ,  Sen Mao ,  Sam Kuo

IPC分类号： G05F3/08 ,  H02M3/04 ,  H05K7/20

CPC分类号： G05F3/08 ,  H01L23/36 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H02M3/00 ,  H02M3/04 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/141 ,  H05K1/181 ,  H05K3/202 ,  H05K3/284 ,  H05K3/3436 ,  H05K7/20409 ,  H05K7/205 ,  H05K2201/10166 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.

摘要翻译： 在单个表面贴装封装中实现的完整的电源管理系统。 该系统可被绘制到DC-DC转换器系统，并且在无引线表面贴装封装中包括驱动器/控制器，MOSFET晶体管，无源元件（例如，电感器，电容器，电阻器）和可选的二极管。 在各种实施例中，MOSFET晶体管可以由绝缘栅双极晶体管，IGBT替代。 该系统还可以是电源管理系统，智能电源模块或运动控制系统。 无源组件可以连接在引线框连接之间。 可以使用金属夹接合技术将有源部件耦合到引线框架。 在一个实施例中，暴露的金属底部可以用作有效散热器。

公开(公告)号：US10546840B2

公开(公告)日：2020-01-28

申请号：US15439817

申请日：2017-02-22

申请人： VISHAY-SILICONIX

发明人： Kyle Terrill ,  Frank Kuo ,  Sen Mao

IPC分类号： H01L25/07 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/544

摘要： In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

公开(公告)号：US10229893B2

公开(公告)日：2019-03-12

申请号：US15457790

申请日：2017-03-13

申请人： VISHAY-SILICONIX

发明人： Frank Kuo ,  Suresh Belani

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

摘要： A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.