公开(公告)号：US09439332B2

公开(公告)日：2016-09-06

申请号：US14237975

申请日：2012-08-09

Applicant: Eiichi Ide ,  Eiji Nishioka ,  Toshiaki Ishii ,  Junpei Kusukawa ,  Kinya Nakatsu ,  Tokihito Suwa

Inventor： Eiichi Ide ,  Eiji Nishioka ,  Toshiaki Ishii ,  Junpei Kusukawa ,  Kinya Nakatsu ,  Tokihito Suwa

IPC: H05K7/20 ,  H01L23/36 ,  H01L23/433 ,  H01L23/495 ,  B60L1/00 ,  B60L3/00 ,  B60L11/12 ,  B60L11/14 ,  B60L15/00 ,  B60L1/02 ,  B60L15/20 ,  H02M7/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/473

CPC classification number: H05K7/209 ,  B60L1/003 ,  B60L1/02 ,  B60L3/003 ,  B60L11/123 ,  B60L11/14 ,  B60L15/007 ,  B60L15/2036 ,  B60L2200/26 ,  B60L2200/42 ,  B60L2210/40 ,  B60L2220/14 ,  B60L2240/12 ,  B60L2240/24 ,  B60L2240/36 ,  B60L2240/421 ,  B60L2240/423 ,  B60L2240/525 ,  B60L2250/16 ,  B60L2250/24 ,  B60L2250/26 ,  B60L2260/28 ,  H01L21/565 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/473 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/37157 ,  H01L2224/3716 ,  H01L2224/3718 ,  H01L2224/3754 ,  H01L2224/40137 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/203 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H02M7/003 ,  H05K7/20927 ,  Y02P90/60 ,  Y02T10/6217 ,  Y02T10/645 ,  Y02T10/7077 ,  Y02T10/7241 ,  Y02T10/7275 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0002 ,  H01L2924/01033 ,  H01L2224/45099

Abstract: A power module includes a sealed body in which a semiconductor chip-mounted conductor plate is sealed by a resin in such a manner that a heat dissipating surface of the conductor plate is exposed, a heat dissipating member that is arranged to face the heat dissipating surface, and an insulation layer that is arranged between the sealed body and the heat dissipating member. The insulation layer has a laminated body that is made by laminating an impregnation resin-impregnated ceramic thermal spray film and a bonding resin layer in which a filler having good thermal conductivity is mixed, and that is provided to be in contact with the heat dissipating member and at least the entirety of the heat dissipating surface, and a stress relief resin portion that is provided in a gap between the heat dissipating member and the sealed body to cover an entire circumferential end portion of the laminated body.

Abstract translation: 功率模块包括密封体，其中半导体芯片安装的导体板以暴露的导体板的散热表面的方式被树脂密封，散热构件被布置成面对散热表面 以及设置在密封体和散热构件之间的绝缘层。 绝缘层具有层叠体，其通过层叠浸渍树脂浸渍的陶瓷热喷涂膜和粘合树脂层而制成，其中混合具有良好导热性的填料，并且被设置成与散热构件接触 以及至少全部的散热面，以及设置在散热构件和密封体之间的间隙中以覆盖层叠体的整个周向端部的应力消除树脂部。

公开(公告)号：US09399268B2

公开(公告)日：2016-07-26

申请号：US14528537

申请日：2014-10-30

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Yuta Tamai

IPC: H01L23/48 ,  B23K26/22 ,  H01L23/00 ,  B23K26/32 ,  H01L23/049 ,  H01L21/48 ,  H01L23/373

CPC classification number: B23K26/206 ,  B23K26/0006 ,  B23K26/037 ,  B23K26/0622 ,  B23K26/211 ,  B23K26/22 ,  B23K26/32 ,  B23K2101/34 ,  B23K2101/35 ,  B23K2101/42 ,  B23K2103/08 ,  B23K2103/10 ,  B23K2103/12 ,  B23K2103/16 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/4846 ,  H01L23/049 ,  H01L23/3735 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40137 ,  H01L2224/75261 ,  H01L2224/7555 ,  H01L2224/83224 ,  H01L2224/83801 ,  H01L2224/83895 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/40102 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In a laser welding method, a gap between first and second members to be welded is made at most 300 μm by pressing the second member against the first member with claws that are pressing parts of a laser welding jig, and the second member to be welded at a place between the claws is irradiated by laser light to laser-weld the first member and the second member. In a semiconductor device, the gap between the first member and the second member at the portion of laser-welding is at most 300 μm.

Abstract translation: 在激光焊接方法中，通过用激光焊接夹具的按压部分的爪将第二构件压靠在第一构件上，待焊接的第一和第二构件之间的间隙最大为300μm，并且待焊接的第二构件 在爪之间的位置用激光照射激光焊接第一部件和第二部件。 在半导体装置中，激光焊接部分的第一部件与第二部件之间的间隙为300μm以下。

公开(公告)号：US09129931B2

公开(公告)日：2015-09-08

申请号：US13989932

申请日：2011-04-27

Applicant: Katsuhiko Omae ,  Mamoru Watanabe ,  Tetsushi Watanabe ,  Yoshihito Asao

Inventor： Katsuhiko Omae ,  Mamoru Watanabe ,  Tetsushi Watanabe ,  Yoshihito Asao

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/371 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/73263 ,  H01L2224/8314 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84138 ,  H01L2224/84801 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A power semiconductor module includes: a plurality of first metal plates arranged in the same planar state; a power semiconductor chip mounted on the first metal plate; and an overbridge-shaped second metal plate which is composed of bridge frame sections and leg sections that support the bridge frame sections, the leg sections being for appropriately performing solder bonding between electrodes of the power semiconductor chips and between the electrode of the power semiconductor chip and the first metal plate, the power semiconductor module being configured by a resin package in which these members are sealed with electrically insulating resin. In the power semiconductor module, the solder bonding section of the leg section is formed in a planar shape by bending process and is provided at a position lower than the bridge frame section.

Abstract translation: 功率半导体模块包括：布置成相同平面状态的多个第一金属板; 安装在所述第一金属板上的功率半导体芯片; 以及跨桥状的第二金属板，其由支撑桥框架部的桥架部和支腿部构成，所述腿部用于适当地进行功率半导体芯片的电极之间和功率半导体芯片的电极之间的焊接 和第一金属板，功率半导体模块由树脂封装构成，其中这些构件用电绝缘树脂密封。 在功率半导体模块中，脚部的焊接部通过弯曲加工形成为平面状，并且设置在比桥框部低的位置。

公开(公告)号：US08952551B2

公开(公告)日：2015-02-10

申请号：US13436039

申请日：2012-03-30

Applicant: Takashi Hisada ,  Katsuyuki Yonehara

Inventor： Takashi Hisada ,  Katsuyuki Yonehara

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/06136 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/84203 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85191 ,  H01L2224/92247 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. Preferably, the conductor plate is composed of a multilayer structure, and each conductor plate is used in power-supply wiring or ground wiring.

Abstract translation: 半导体封装包括布线基板，半导体芯片和导体板，以便减少由设置在芯片周围的外围连接焊盘引起的布线电阻引起的芯片中心部分的电压降。 用于接地/供电的中央电极焊盘设置在芯片的中心部分。 用于接地/供电的导体板设置在芯片上，使得绝缘层位于它们之间。 芯片和导体板上的中心电极焊盘通过形成在绝缘层和导体板中的开口进行引线接合而连接在一起。 导体板的提取部分连接到布线基板上的电源布线焊盘。 优选地，导体板由多层结构构成，并且每个导体板用于电源布线或接地布线。

公开(公告)号：US08710666B2

公开(公告)日：2014-04-29

申请号：US12801603

申请日：2010-06-16

Applicant: Junji Tsuruoka ,  Kazuo Aoki ,  Masaki Ono ,  Katsuhiko Yoshihara

Inventor： Junji Tsuruoka ,  Kazuo Aoki ,  Masaki Ono ,  Katsuhiko Yoshihara

IPC: H01L23/498

CPC classification number: H01L23/24 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/072 ,  H01L2224/32225 ,  H01L2224/371 ,  H01L2224/3754 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/4903 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2224/37099

Abstract: A semiconductor device which can prevent a deterioration in the electrical properties by preventing sputters generated by laser welding from adhering to a circuit pattern or a semiconductor chip and a method for fabricating such a semiconductor device are provided. A connection conductor is bonded to a copper foil formed over a ceramic by a solder and resin is injected to a level lower than a top of the connection conductor. Laser welding is then performed. After that, resin is injected. This prevents sputters generated by the laser welding from adhering to a circuit pattern or a semiconductor chip. As a result, a deterioration in the electrical properties can be prevented.

Abstract translation: 提供一种可以通过防止由激光焊接产生的喷溅物粘附到电路图案或半导体芯片来防止电性能劣化的半导体器件，以及制造这种半导体器件的方法。 连接导体通过焊料与陶瓷上形成的铜箔接合，并且将树脂注入到比连接导体的顶部低的水平。 然后进行激光焊接。 之后，注入树脂。 这防止由激光焊接产生的喷溅物粘附到电路图案或半导体芯片。 结果，可以防止电性能的劣化。

公开(公告)号：US08642394B2

公开(公告)日：2014-02-04

申请号：US12020821

申请日：2008-01-28

Applicant: Abdul Rahman Mohamed ,  Stanley Job Doraisamy ,  Tien Lai Tan ,  Ralf Otremba

Inventor： Abdul Rahman Mohamed ,  Stanley Job Doraisamy ,  Tien Lai Tan ,  Ralf Otremba

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/49562 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/73153 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/83399 ,  H01L2224/83439 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/0715 ,  H01L2924/07025 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01049 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device and method of manufacturing. One embodiment includes attaching a first semiconductor chip to a first metallic clip. The first semiconductor chip is placed over a leadframe after the attachment of the first semiconductor chip to the first metallic clip.

Abstract translation: 一种电子设备及其制造方法。 一个实施例包括将第一半导体芯片附接到第一金属夹。 在将第一半导体芯片附接到第一金属夹子之后，第一半导体芯片放置在引线框架上。

公开(公告)号：US08629499B2

公开(公告)日：2014-01-14

申请号：US13481937

申请日：2012-05-28

Applicant: Ahmad Ashrafzadeh

Inventor： Ahmad Ashrafzadeh

IPC: H01L29/66

CPC classification number: H01L29/7802 ,  H01L23/041 ,  H01L23/481 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L25/072 ,  H01L29/42372 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/73153 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/16152 ,  H01L2924/167 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.

Abstract translation: MOSFET功率芯片包括第一垂直MOSFET和第二垂直MOSFET。 第一垂直MOSFET包括具有限定源极的第一表面和限定漏极的第二表面和形成在半导体本体中靠近第二表面的栅极结构的半导体本体。 通孔形成在半导体本体内并且基本上垂直于第一表面和第二表面。 通孔具有电耦合到第一表面的第一端和电耦合到栅极结构的第二端。 第二垂直MOSFET包括半导体本体，其具有限定源极的第一表面，限定漏极的第二表面和形成在第一表面附近的半导体本体中的栅极结构。

公开(公告)号：US08619825B2

公开(公告)日：2013-12-31

申请号：US12706833

申请日：2010-02-17

Applicant: Hiroyuki Fukasawa ,  Hiroshi Nishida

Inventor： Hiroyuki Fukasawa ,  Hiroshi Nishida

IPC: H01S3/04 ,  H01S3/042

CPC classification number: H01S3/0405 ,  H01L23/055 ,  H01L24/34 ,  H01L24/37 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/48463 ,  H01L2224/48472 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/10349 ,  H01L2924/12043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01S5/02212 ,  H01S5/0224 ,  H01S5/02264 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/02476 ,  H01S5/4043 ,  H01S5/4087 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light-emitting device reliably supplying electric power to a light-emitting element on a supporting base and securing heat dissipation, and a method of manufacturing the light-emitting device are provided. A light-emitting device includes: a light-emitting element arranged on a first supporting base; a package covering the first supporting base and the light-emitting element therewith, and supporting the first supporting base; and a thermal conductive member having ends which are bonded to the light-emitting element and the package, respectively, so as to also have a wiring function.

Abstract translation: 一种可靠地向支撑基座上的发光元件提供电力并确保散热的发光装置，以及制造该发光装置的方法。 发光装置包括：配置在第一支撑基座上的发光元件; 封装所述第一支撑基座和所述发光元件的封装，并支撑所述第一支撑基座; 以及分别具有接合到发光元件和封装的端部的导热构件，以便也具有布线功能。

公开(公告)号：US20120292691A1

公开(公告)日：2012-11-22

申请号：US13481937

申请日：2012-05-28

Applicant: Ahmad Ashrafzadeh

Inventor： Ahmad Ashrafzadeh

IPC: H01L29/78

CPC classification number: H01L29/7802 ,  H01L23/041 ,  H01L23/481 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L25/072 ,  H01L29/42372 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/73153 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/16152 ,  H01L2924/167 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.

Abstract translation: MOSFET功率芯片包括第一垂直MOSFET和第二垂直MOSFET。 第一垂直MOSFET包括具有限定源极的第一表面和限定漏极的第二表面和形成在半导体本体中靠近第二表面的栅极结构的半导体本体。 通孔形成在半导体本体内并且基本上垂直于第一表面和第二表面。 通孔具有电耦合到第一表面的第一端和电耦合到栅极结构的第二端。 第二垂直MOSFET包括半导体本体，其具有限定源极的第一表面，限定漏极的第二表面和形成在第一表面附近的半导体本体中的栅极结构。

公开(公告)号：US08193622B2

公开(公告)日：2012-06-05

申请号：US12717012

申请日：2010-03-03

Applicant: Ruben P. Madrid

Inventor： Ruben P. Madrid

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L24/33 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/544 ,  H01L24/37 ,  H01L24/40 ,  H01L24/81 ,  H01L24/83 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package.

Abstract translation: 公开了一种半导体管芯封装。 半导体管芯封装包括半导体管芯，其包括在第一顶部半导体管芯表面处的输入端和在第二下部半导体管芯表面处的输出端。 具有第一引线框架表面和与第一引线框架表面相对的第二引线框架表面的引线框架在半导体管芯封装中并且耦合到第一顶部半导体管芯表面。 具有第一夹子表面和第二夹子表面的夹子联接到第二底部半导体管芯表面。 具有外部成型材料表面的成型材料覆盖引线框，夹子和半导体管芯的至少一部分。 第一引线框架表面和第一夹子表面被模制材料暴露，并且第一引线框架表面，第一夹子表面和模制材料的外部模制材料表面形成半导体管芯封装的外表面。