-
公开(公告)号：US11908780B2
公开(公告)日：2024-02-20
申请号：US17518554
申请日：2021-11-03
CPC分类号： H01L23/49575 , H01L23/49513 , H01L23/49562 , H01L24/32 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/92 , H01L25/074 , H01L25/16 , H01L25/50 , H01L21/561 , H01L21/565 , H01L23/3121 , H01L24/97 , H01L2224/32245 , H01L2224/40145 , H01L2224/40177 , H01L2224/4118 , H01L2224/48091 , H01L2224/48106 , H01L2224/48137 , H01L2224/48247 , H01L2224/73221 , H01L2224/73263 , H01L2224/83815 , H01L2224/84815 , H01L2224/92246 , H01L2924/13091 , H01L2924/1426 , H01L2924/2064
摘要： A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.
-
公开(公告)号：US09093900B2
公开(公告)日：2015-07-28
申请号：US13933681
申请日：2013-07-02
发明人： Timothy J. Hegarty
IPC分类号： G05F1/00 , H02M3/158 , H01L23/495 , H01L23/00 , H02M1/00
CPC分类号： H02M3/158 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L2224/05553 , H01L2224/05554 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/4118 , H01L2224/48247 , H01L2224/73221 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/30107 , H02M2001/0009 , H01L2924/00 , H01L2224/45099 , H01L2224/84
摘要： One embodiment includes a power regulator system. The system includes a gate driver circuit configured to generate switching signal and a switching circuit package configured to receive the switching signal at a gate terminal. A signal return associated with the switching signal is provided at a gate return terminal. The switching circuit package also includes a switch that is periodically activated in response to the switching signal to generate a switching voltage at a switching node terminal. A filter stage includes an inductor interconnecting the switching node terminal and a node. The inductor can be configured to conduct a current in response to the switching voltage to generate an output voltage. A current sense circuit interconnects the gate return terminal and the node and measures a magnitude of the output current.
摘要翻译： 一个实施例包括功率调节器系统。 该系统包括被配置为产生开关信号的栅极驱动器电路和被配置为在栅极端子处接收切换信号的开关电路封装。 与开关信号相关联的信号返回被提供在门极返回端子处。 开关电路封装还包括响应于开关信号周期性地激活以在开关节点端产生开关电压的开关。 滤波器级包括将开关节点端子和节点互连的电感器。 电感器可以被配置为响应于开关电压导通电流以产生输出电压。 电流检测电路将栅极返回端子和节点互连，并测量输出电流的大小。
-
公开(公告)号：US08686546B2
公开(公告)日：2014-04-01
申请号：US13077720
申请日：2011-03-31
申请人： Yueh-Se Ho , Hamza Yilmaz , Yan Xun Xue , Jun Lu
发明人： Yueh-Se Ho , Hamza Yilmaz , Yan Xun Xue , Jun Lu
IPC分类号： H01L23/495 , H01L23/02
CPC分类号： H01L23/49524 , H01L23/3107 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/84 , H01L25/074 , H01L25/18 , H01L2224/0401 , H01L2224/05553 , H01L2224/05599 , H01L2224/32245 , H01L2224/33181 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/4118 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48177 , H01L2224/48247 , H01L2224/48257 , H01L2224/49111 , H01L2224/49171 , H01L2224/73221 , H01L2224/8385 , H01L2224/8485 , H01L2224/85399 , H01L2224/92 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2224/81 , H01L2224/84 , H01L2224/45099 , H01L2924/00 , H01L2224/13099 , H01L2224/13599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012
摘要： A combined packaged power semiconductor device includes a flipped top source low-side MOSFET electrically connected to a top surface of a die paddle, a first metal interconnection plate connecting between a bottom drain of a high-side MOSFET or a top source of a flipped high-side MOSFET to a bottom drain of the low-side MOSFET, and a second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally that reduces the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.
摘要翻译： 组合封装的功率半导体器件包括电连接到管芯焊盘的顶表面的翻转顶部源极低侧MOSFET，连接在高侧MOSFET的底部漏极或翻转高电平的顶部源的第一金属互连板 的低端MOSFET的底部漏极和堆叠在高侧MOSFET芯片的顶部上的第二金属互连板。 高侧，低端MOSFET和IC控制器可以三维封装，从而减小半导体器件的总体尺寸，并可在相同尺寸的封装内最大限度地提高芯片的尺寸，并提高半导体器件的性能。 翻转的低侧MOSFET的顶部源极连接到管芯焊盘的顶表面，并且因此通过裸片的裸露的底表面接地，这简化了裸片焊盘的暴露的底面的形状，并使面积最大化 散热。
-
公开(公告)号：US20140028272A1
公开(公告)日：2014-01-30
申请号：US13933681
申请日：2013-07-02
发明人： TIMOTHY J. HEGARTY
IPC分类号： H02M3/158
CPC分类号： H02M3/158 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L2224/05553 , H01L2224/05554 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/4118 , H01L2224/48247 , H01L2224/73221 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/30107 , H02M2001/0009 , H01L2924/00 , H01L2224/45099 , H01L2224/84
摘要： One embodiment includes a power regulator system. The system includes a gate driver circuit configured to generate switching signal and a switching circuit package configured to receive the switching signal at a gate terminal. A signal return associated with the switching signal is provided at a gate return terminal. The switching circuit package also includes a switch that is periodically activated in response to the switching signal to generate a switching voltage at a switching node terminal. A filter stage includes an inductor interconnecting the switching node terminal and a node. The inductor can be configured to conduct a current in response to the switching voltage to generate an output voltage. A current sense circuit interconnects the gate return terminal and the node and measures a magnitude of the output current.
摘要翻译： 一个实施例包括功率调节器系统。 该系统包括被配置为产生开关信号的栅极驱动器电路和被配置为在栅极端子处接收切换信号的开关电路封装。 与开关信号相关联的信号返回被提供在门极返回端子处。 开关电路封装还包括响应于开关信号周期性地激活以在开关节点端产生开关电压的开关。 滤波器级包括将开关节点端子和节点互连的电感器。 电感器可以被配置为响应于开关电压导通电流以产生输出电压。 电流检测电路将栅极返回端子和节点互连，并测量输出电流的大小。
-
公开(公告)号：US20170148711A1
公开(公告)日：2017-05-25
申请号：US15426205
申请日：2017-02-07
发明人： Francois HEBERT
IPC分类号： H01L23/495 , H01L29/10 , H01L29/78
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/4951 , H01L23/49513 , H01L23/49537 , H01L23/49541 , H01L23/49562 , H01L23/49568 , H01L23/49582 , H01L24/37 , H01L24/40 , H01L24/41 , H01L29/1095 , H01L29/7809 , H01L29/781 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/0603 , H01L2224/16145 , H01L2224/16245 , H01L2224/32245 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40475 , H01L2224/4103 , H01L2224/41051 , H01L2224/4118 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2224/73207 , H01L2224/73221 , H01L2224/73253 , H01L2224/73263 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.
-
6.发明授权Packaging solutions for devices and systems comprising lateral GaN power transistors 有权包括横向GaN功率晶体管的器件和系统的封装解决方案公开(公告)号：US09589868B2
公开(公告)日：2017-03-07
申请号：US15064750
申请日：2016-03-09
申请人： GaN Systems Inc.
IPC分类号： H01L23/00 , H01L23/495 , H01L23/31 , H01L21/56 , H01L21/78 , H01L23/498 , H01L23/492 , H01L23/482
CPC分类号： H01L23/49503 , H01L21/565 , H01L21/78 , H01L23/3107 , H01L23/4824 , H01L23/492 , H01L23/4952 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L23/49861 , H01L24/02 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/84 , H01L24/92 , H01L24/97 , H01L2224/0239 , H01L2224/131 , H01L2224/13147 , H01L2224/16245 , H01L2224/245 , H01L2224/291 , H01L2224/29139 , H01L2224/2929 , H01L2224/29339 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/352 , H01L2224/37012 , H01L2224/37013 , H01L2224/37147 , H01L2224/40227 , H01L2224/40245 , H01L2224/40475 , H01L2224/40499 , H01L2224/41051 , H01L2224/4118 , H01L2224/73203 , H01L2224/73263 , H01L2224/81132 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/81447 , H01L2224/81801 , H01L2224/81815 , H01L2224/83447 , H01L2224/83801 , H01L2224/83815 , H01L2224/8384 , H01L2224/84801 , H01L2224/84815 , H01L2224/8484 , H01L2224/92143 , H01L2224/97 , H01L2924/00015 , H01L2924/01014 , H01L2924/04642 , H01L2924/1033 , H01L2924/13064 , H01L2924/13091 , H01L2924/17747 , H01L2924/014 , H01L2924/00014 , H01L2924/01029 , H01L2924/01047 , H01L2924/00012 , H01L2924/0665 , H01L2224/83 , H01L2224/84 , H01L2224/81 , H01L2224/48
摘要： Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.
摘要翻译： 公开了用于大面积的包括一个或多个横向GaN功率晶体管器件和系统的GaN管芯的封装解决方案。 包装组件包括包括横向GaN管芯和引线框架的插入件子组件。 GaN管芯使用凸点或柱互连，银烧结或其他低电感互连电连接到引线框架。 然后，在单个工艺步骤中制造GaN管芯到衬底的连接以及引线框架与衬底上的触点的电连接。 子组件可以安装在标准功率模块中，或者替代地安装在诸如印刷电路板的基板上。 对于高电流应用，子组件还包括用于散热的陶瓷衬底。 与传统的引线键合功率模块相比，该封装方案提供了具有较低电感和较高电流容量的互连，简化了制造，并且能够改进组件的热匹配。
-
公开(公告)号：US20150221581A1
公开(公告)日：2015-08-06
申请号：US14475438
申请日：2014-09-02
发明人： Koji TAMURA
IPC分类号： H01L23/495 , H01L23/00 , H01L21/56 , H01L23/31
CPC分类号： H01L23/49513 , H01L21/56 , H01L21/565 , H01L23/3107 , H01L23/3142 , H01L23/49531 , H01L23/49537 , H01L23/49541 , H01L23/49548 , H01L23/49551 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/83 , H01L24/84 , H01L24/92 , H01L2224/27312 , H01L2224/291 , H01L2224/29294 , H01L2224/29339 , H01L2224/32245 , H01L2224/3226 , H01L2224/33181 , H01L2224/352 , H01L2224/37012 , H01L2224/37013 , H01L2224/37147 , H01L2224/40499 , H01L2224/41051 , H01L2224/4118 , H01L2224/48245 , H01L2224/73215 , H01L2224/73221 , H01L2224/73265 , H01L2224/73271 , H01L2224/8314 , H01L2224/83191 , H01L2224/83192 , H01L2224/832 , H01L2224/83203 , H01L2224/8321 , H01L2224/83447 , H01L2224/838 , H01L2224/83801 , H01L2224/83815 , H01L2224/84138 , H01L2224/84203 , H01L2224/8421 , H01L2224/84801 , H01L2224/84815 , H01L2224/92242 , H01L2924/00014 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/45099 , H01L2224/27
摘要： According to one embodiment, a first frame includes a first thin plate section and a first thick plate section. A second frame includes a second thin plate section and a second thick plate section. A semiconductor chip includes a first electrode bonded to a first inner surface of the first thin plate section of the first frame, and a second electrode bonded to a second inner surface of the second thick plate section of the second frame. A resin layer seals the semiconductor chip, but leaves exposed the first outer surface of the first frame and the second outer surface of the second frame.
摘要翻译： 根据一个实施例，第一框架包括第一薄板部分和第一厚板部分。 第二框架包括第二薄板部分和第二厚板部分。 半导体芯片包括接合到第一框架的第一薄板部分的第一内表面的第一电极和结合到第二框架的第二厚板部分的第二内表面的第二电极。 树脂层密封半导体芯片，但是露出第一框架的第一外表面和第二框架的第二外表面。
-
公开(公告)号：US20140273344A1
公开(公告)日：2014-09-18
申请号：US13830041
申请日：2013-03-14
申请人： VISHAY-SILICONIX
发明人： Kyle TERRILL , Frank KUO , Sen MAO
IPC分类号： H01L23/00
CPC分类号： H01L25/074 , H01L21/4853 , H01L21/565 , H01L21/566 , H01L23/3107 , H01L23/3157 , H01L23/49513 , H01L23/49524 , H01L23/49541 , H01L23/49568 , H01L23/49575 , H01L23/49844 , H01L23/544 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/85 , H01L24/92 , H01L2223/54486 , H01L2224/27318 , H01L2224/2732 , H01L2224/291 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/32245 , H01L2224/33181 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40499 , H01L2224/4103 , H01L2224/41051 , H01L2224/41052 , H01L2224/411 , H01L2224/41105 , H01L2224/4118 , H01L2224/48091 , H01L2224/48105 , H01L2224/48245 , H01L2224/48247 , H01L2224/49052 , H01L2224/49105 , H01L2224/73263 , H01L2224/73265 , H01L2224/73271 , H01L2224/83191 , H01L2224/83192 , H01L2224/83801 , H01L2224/83815 , H01L2224/8385 , H01L2224/83851 , H01L2224/8391 , H01L2224/84801 , H01L2224/84815 , H01L2224/8485 , H01L2224/8491 , H01L2224/9221 , H01L2224/92246 , H01L2224/92252 , H01L2924/00014 , H01L2924/00015 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2224/48 , H01L2924/014 , H01L2924/00012 , H01L2924/0665 , H01L2924/07811 , H01L2224/85 , H01L2224/45099 , H01L2224/05599
摘要： In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.
摘要翻译： 在一个实施例中，一种方法可以包括将第一管芯的栅极和源极耦合到引线框架。 第一管芯可以包括位于第一管芯的第一表面上的栅极和源极，以及位于第一管芯的与第一表面相对的第二表面上的漏极。 此外，该方法可以包括将第二管芯的源耦合到第一管芯的漏极。 第二管芯可以包括位于第二管芯的第一表面上的栅极和漏极，以及位于第二管芯的与第一表面相对的第二表面上的源极。
-
9.发明公开公开(公告)号：US20240312882A1
公开(公告)日：2024-09-19
申请号：US18671243
申请日：2024-05-22
发明人： Junqing HE , Mohuai CHANG , Yanqiu LI , Wentao YANG
IPC分类号： H01L23/495 , H01L23/00 , H01L23/06 , H01L25/065
CPC分类号： H01L23/49575 , H01L23/06 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/73 , H01L25/0657 , H01L2224/32245 , H01L2224/37005 , H01L2224/40145 , H01L2224/40175 , H01L2224/41176 , H01L2224/4118 , H01L2224/73263
摘要： A chip package module, including a first conductive frame, a first bare die disposed on the first conductive frame, and a second conductive frame disposed at an interval beside the first conductive frame. The chip package module further includes a first conductive connecting sheet, a second bare die, and a conductive cover plate. The first conductive connecting sheet is connected to a surface of the first bare die away from the first conductive frame, and extends to be lapped on the second conductive frame. The second bare die is laminated on the first bare die and is connected to the first conductive connecting sheet. The conductive cover plate is connected to a surface of the second bare die away from the first conductive frame and extends to be connected to the first conductive frame.
-
公开(公告)号：US09991192B2
公开(公告)日：2018-06-05
申请号：US15426205
申请日：2017-02-07
发明人： Francois Hebert
IPC分类号： H01L21/00 , H01L23/495 , H01L29/78 , H01L29/10
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/4951 , H01L23/49513 , H01L23/49537 , H01L23/49541 , H01L23/49562 , H01L23/49568 , H01L23/49582 , H01L24/37 , H01L24/40 , H01L24/41 , H01L29/1095 , H01L29/7809 , H01L29/781 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/0603 , H01L2224/16145 , H01L2224/16245 , H01L2224/32245 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40475 , H01L2224/4103 , H01L2224/41051 , H01L2224/4118 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2224/73207 , H01L2224/73221 , H01L2224/73253 , H01L2224/73263 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.014 秒)
