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公开(公告)号：US09761501B2
公开(公告)日：2017-09-12
申请号：US14783851
申请日：2013-04-11
CPC分类号： H01L22/14 , G01R1/0466 , G01R1/0483 , G01R1/06738 , G01R31/2874 , G01R31/40 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/97 , H01L25/50 , H01L2224/32245 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/48137 , H01L2224/48247 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2224/97 , H01L2924/00014 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/37099
摘要： Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
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公开(公告)号：US10141295B2
公开(公告)日：2018-11-27
申请号：US15730977
申请日：2017-10-12
发明人： Bunji Yasumura , Yoshinori Deguchi , Fumikazu Takei , Akio Hasebe , Naohiro Makihira , Mitsuyuki Kubo
IPC分类号： H01L21/30 , H01L25/00 , H01L21/683 , H01L23/00 , H01L21/66 , H01L23/544 , H01L25/065 , H01L25/18
摘要： To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
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公开(公告)号：US09905482B2
公开(公告)日：2018-02-27
申请号：US15672547
申请日：2017-08-09
CPC分类号： H01L22/14 , G01R1/0466 , G01R1/0483 , G01R1/06738 , G01R31/2874 , G01R31/40 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/97 , H01L25/50 , H01L2224/32245 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/48137 , H01L2224/48247 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2224/97 , H01L2924/00014 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/37099
摘要： Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
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公开(公告)号：US08945953B2
公开(公告)日：2015-02-03
申请号：US14133614
申请日：2013-12-18
发明人： Akio Hasebe , Naohiro Makihira , Bunji Yasumura , Mitsuyuki Kubo , Fumikazu Takei , Yoshinori Deguchi
IPC分类号： H01L21/66
CPC分类号： H01L24/89 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L21/78 , H01L22/14 , H01L23/481 , H01L23/49816 , H01L23/50 , H01L23/5226 , H01L24/05 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2221/68327 , H01L2221/6834 , H01L2221/68368 , H01L2224/0401 , H01L2224/05025 , H01L2224/05568 , H01L2224/05624 , H01L2224/08235 , H01L2224/1146 , H01L2224/13023 , H01L2224/13025 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/73204 , H01L2224/8036 , H01L2224/8085 , H01L2224/81801 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/381 , H01L2924/00014 , H01L2924/014 , H01L2924/00 , H01L2924/00012
摘要： Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.
摘要翻译： 提供了一种制造半导体器件的方法，该半导体器件包括测试每个通孔的步骤。 进行第二探针测试以检查形成在晶片表面一侧的多个铜柱形凸块之间的电耦合状态，并且电耦合到金属层和形成在背面侧的多个凸点 并且通过探测背面一侧的每个凸块，同时在铜柱凸起（电极）之间短路，通过多个通孔电耦合到金属层（也是另一金属层）。 通过该测试，检查背面侧的凸块（电极）之间的导通。
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公开(公告)号：US10551432B2
公开(公告)日：2020-02-04
申请号：US15954657
申请日：2018-04-17
摘要： A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.
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公开(公告)号：US09945903B2
公开(公告)日：2018-04-17
申请号：US15151152
申请日：2016-05-10
IPC分类号： H01L21/66 , G01R31/28 , H01L21/56 , H01L21/67 , H01L23/495 , H01L23/00 , H01L23/31 , H01L23/544
CPC分类号： G01R31/2884 , G01R31/44 , H01L21/56 , H01L21/67242 , H01L23/3121 , H01L23/49541 , H01L23/49575 , H01L23/544 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2223/54433 , H01L2223/54486 , H01L2224/04042 , H01L2224/05014 , H01L2224/05554 , H01L2224/29101 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48101 , H01L2224/48106 , H01L2224/48137 , H01L2224/48245 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/48471 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2224/92247 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01083 , H01L2924/014 , H01L2924/15747 , H01L2924/17747 , H01L2924/181 , H01L2924/19042 , H01L2924/00012 , H01L2224/05599 , H01L2924/00
摘要： This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.
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公开(公告)号：US09515000B2
公开(公告)日：2016-12-06
申请号：US14929252
申请日：2015-10-30
CPC分类号： H01L22/14 , G01R1/0466 , G01R1/06716 , G01R1/07357 , G01R31/2601 , H01L21/565 , H01L22/30 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.
摘要翻译： 通过接触销与外部端子的多点接触的可靠性得到改善，同时实现了接触销的制造容易度的提高。 接触针包括第一和第二接触针。 此外，第一接触销具有沿y方向延伸的支撑部分和连接到支撑部分的尖端部分。 第二接触销还具有在y方向上延伸的支撑部分和连接到支撑部分的尖端部分。 这里，第一接触销的支撑部分和第二接触销的支撑部分在水平面（xy平面）中沿x方向并排设置。 此外，第二接触销的前端部沿着与x方向交叉（垂直于）方向的水平面的y方向从第一接触销的前端部移位。
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公开(公告)号：US20160064291A1
公开(公告)日：2016-03-03
申请号：US14783851
申请日：2013-04-11
CPC分类号： H01L22/14 , G01R1/0466 , G01R1/0483 , G01R1/06738 , G01R31/2874 , G01R31/40 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/97 , H01L25/50 , H01L2224/32245 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/48137 , H01L2224/48247 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2224/97 , H01L2924/00014 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/37099
摘要： Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
摘要翻译： 获得半导体器件的产量的提高。 另外，可以获得插座端子的使用寿命的增加。 突出部PJ1和突出部PJ2设置在插座端子STE1的端部PU中。 因此，例如，可以通过使用突出部PJ1的触点和通过使用突出部PJ2的触点在两点处使引线和引起大电流的插座端子STE之间的接触。 结果，从插座端子STE1流向引线的电流通过分散到在突出部分PJ1中流动的路径和在突出部分PJ2中流动的路径而流动。 因此，即使在插座端子STE1和引线之间流动大电流的情况下，也可以抑制插座端子STE1和引线之间的接触部分的温度升高。
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公开(公告)号：US10109568B2
公开(公告)日：2018-10-23
申请号：US15674491
申请日：2017-08-10
IPC分类号： H01L23/00 , H01L23/498 , H01L21/56 , H01L21/78 , H01L21/66
摘要： The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball.
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公开(公告)号：US09053954B2
公开(公告)日：2015-06-09
申请号：US14194874
申请日：2014-03-03
发明人： Bunji Yasumura , Yoshinori Deguchi , Fumikazu Takei , Akio Hasebe , Naohiro Makihira , Mitsuyuki Kubo
IPC分类号： H01L21/30 , H01L25/065 , H01L23/544 , H01L21/66
CPC分类号： H01L25/50 , H01L21/6835 , H01L22/12 , H01L22/14 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2221/68327 , H01L2223/54426 , H01L2223/5448 , H01L2223/54493 , H01L2224/03002 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/06131 , H01L2224/11009 , H01L2224/13025 , H01L2224/13082 , H01L2224/13147 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06593 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/16251 , H01L2924/181 , H01L2224/11 , H01L2924/00
摘要： To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
摘要翻译： 提高半导体器件的组装性。 当存储器芯片安装在逻辑芯片上时，将形成在逻辑芯片的背面的识别标记的识别范围成像，识别范围的形状，逻辑芯片的多个凸点与 基于识别的结果执行上述存储芯片的多个投影电极，并且将上述存储芯片安装在逻辑芯片上。 此时，识别范围的形状与凸块的阵列形状的任何部分不同，结果，可以可靠地识别识别范围形状的识别标记，并且逻辑的凸块的对准 高精度地执行上述存储芯片的芯片和投影电极。
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