公开(公告)号：US20150187691A1

公开(公告)日：2015-07-02

申请号：US14408887

申请日：2013-06-25

Applicant: Research Triangle Institute

Inventor： Eric Paul Vick

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/02107 ,  H01L21/76898 ,  H01L24/24 ,  H01L24/29 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/80203 ,  H01L2224/8036 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/83203 ,  H01L2224/8336 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/0675 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/80001 ,  H01L2224/82 ,  H05K3/4661 ,  H01L2224/83

Abstract: An electronic package may be fabricated by forming a first layer of insulating material on a first substrate such that the first layer covers a contact pad; forming an opening through the first layer to expose the contact pad; forming an un-patterned second layer on the first layer, the second layer including an adhesive having a viscosity less than that of the first layer, wherein a region of the second layer obstructs the contact pad; removing the region to re-expose the contact pad; aligning a second substrate with the first substrate such that a via of the second substrate is aligned with the opening; bonding the first substrate and the second substrate together at the second layer; and forming an interconnect in contact with the contact pad by depositing a conductive material through the via and the opening.

Abstract translation: 可以通过在第一基板上形成第一绝缘材料层来制造电子封装，使得第一层覆盖接触垫; 通过所述第一层形成开口以暴露所述接触垫; 在所述第一层上形成未图案化的第二层，所述第二层包括粘度小于所述第一层粘度的粘合剂，其中所述第二层的区域阻碍所述接触垫; 去除区域以重新暴露接触垫; 将第二基板与第一基板对准，使得第二基板的通孔与开口对准; 在第二层将第一基板和第二基板接合在一起; 以及通过通过所述通孔和所述开口沉积导电材料来形成与所述接触焊盘接触的互连。

公开(公告)号：US08945953B2

公开(公告)日：2015-02-03

申请号：US14133614

申请日：2013-12-18

Applicant: Renesas Electronics Corporation

Inventor： Akio Hasebe ,  Naohiro Makihira ,  Bunji Yasumura ,  Mitsuyuki Kubo ,  Fumikazu Takei ,  Yoshinori Deguchi

IPC: H01L21/66

CPC classification number: H01L24/89 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/08235 ,  H01L2224/1146 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/8036 ,  H01L2224/8085 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

Abstract translation: 提供了一种制造半导体器件的方法，该半导体器件包括测试每个通孔的步骤。 进行第二探针测试以检查形成在晶片表面一侧的多个铜柱形凸块之间的电耦合状态，并且电耦合到金属层和形成在背面侧的多个凸点 并且通过探测背面一侧的每个凸块，同时在铜柱凸起（电极）之间短路，通过多个通孔电耦合到金属层（也是另一金属层）。 通过该测试，检查背面侧的凸块（电极）之间的导通。

公开(公告)号：US20150111317A1

公开(公告)日：2015-04-23

申请号：US14583693

申请日：2014-12-27

Applicant: Renesas Electronics Corporation

Inventor： Akio Hasebe ,  Naohiro Makihira ,  Bunji Yasumura ,  Mitsuyuki Kubo ,  Fumikazu Takei ,  Yoshinori Deguchi

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L21/66

CPC classification number: H01L24/89 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/08235 ,  H01L2224/1146 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/8036 ,  H01L2224/8085 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

Abstract translation: 提供了一种制造半导体器件的方法，该半导体器件包括测试每个通孔的步骤。 进行第二探针测试以检查形成在晶片表面一侧的多个铜柱形凸块之间的电耦合状态，并且电耦合到金属层和形成在背面侧的多个凸点 并且通过探测背面一侧的每个凸块，同时在铜柱凸起（电极）之间短路，通过多个通孔电耦合到金属层（也是另一金属层）。 通过该测试，检查背面侧的凸块（电极）之间的导通。

公开(公告)号：US20140179032A1

公开(公告)日：2014-06-26

申请号：US14133614

申请日：2013-12-18

Applicant: Renesas Electronics Corporation

Inventor： Akio Hasebe ,  Naohiro Makihira ,  Bunji Yasumura ,  Mitsuyuki Kubo ,  Fumikazu Takei ,  Yoshinori Deguchi

IPC: H01L21/66

CPC classification number: H01L24/89 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/08235 ,  H01L2224/1146 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/8036 ,  H01L2224/8085 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

Abstract translation: 提供了一种制造半导体器件的方法，该半导体器件包括测试每个通孔的步骤。 进行第二探针测试以检查形成在晶片表面一侧的多个铜柱形凸块之间的电耦合状态，并且电耦合到金属层和形成在背面侧的多个凸点 并且通过探测背面一侧的每个凸块，同时在铜柱凸起（电极）之间短路，通过多个通孔电耦合到金属层（也是另一金属层）。 通过该测试，检查背面侧的凸块（电极）之间的导通。

公开(公告)号：US09576889B2

公开(公告)日：2017-02-21

申请号：US14408887

申请日：2013-06-25

Applicant: Research Triangle Institute

Inventor： Erik Paul Vick

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/02 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/49827 ,  H01L21/02107 ,  H01L21/76898 ,  H01L24/24 ,  H01L24/29 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/80203 ,  H01L2224/8036 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/83203 ,  H01L2224/8336 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/0675 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/80001 ,  H01L2224/82 ,  H05K3/4661 ,  H01L2224/83

Abstract: An electronic package may be fabricated by forming a first layer of insulating material on a first substrate such that the first layer covers a contact pad; forming an opening through the first layer to expose the contact pad; forming an un-patterned second layer on the first layer, the second layer including an adhesive having a viscosity less than that of the first layer, wherein a region of the second layer obstructs the contact pad; removing the region to re-expose the contact pad; aligning a second substrate with the first substrate such that a via of the second substrate is aligned with the opening; bonding the first substrate and the second substrate together at the second layer; and forming an interconnect in contact with the contact pad by depositing a conductive material through the via and the opening.

Abstract translation: 可以通过在第一基板上形成第一绝缘材料层来制造电子封装，使得第一层覆盖接触垫; 通过所述第一层形成开口以暴露所述接触垫; 在所述第一层上形成未图案化的第二层，所述第二层包括粘度小于所述第一层粘度的粘合剂，其中所述第二层的区域阻碍所述接触垫; 去除区域以重新暴露接触垫; 将第二基板与第一基板对准，使得第二基板的通孔与开口对准; 在第二层将第一基板和第二基板接合在一起; 以及通过通过所述通孔和所述开口沉积导电材料来形成与所述接触焊盘接触的互连。

公开(公告)号：US09230938B2

公开(公告)日：2016-01-05

申请号：US14583693

申请日：2014-12-27

Applicant: Renesas Electronics Corporation

Inventor： Akio Hasebe ,  Naohiro Makihira ,  Bunji Yasumura ,  Mitsuyuki Kubo ,  Fumikazu Takei ,  Yoshinori Deguchi

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L25/18 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L24/89 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/08235 ,  H01L2224/1146 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/8036 ,  H01L2224/8085 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

公开(公告)号：US09230941B2

公开(公告)日：2016-01-05

申请号：US14229114

申请日：2014-03-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Szu-Ying Chen ,  Dun-Nian Yaung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L24/89 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0382 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/09515 ,  H01L2224/09517 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/8034 ,  H01L2224/80357 ,  H01L2224/8036 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/80001

Abstract: A semiconductor device, and a method of fabrication, is introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and a first bonding pad, a second bonding pad, and a first via are formed in the recesses. In some embodiment, the first via may have electrical contact with the first bonding pad and may provide an electrical pathway to a first plurality of metallization layers. The first bonding pad and the second bonding pad in the first substrate are aligned to a third bonding pad and the fourth bonding pad in a second substrate and may be bonded using a direct bonding method. A bond between the first bonding pad and the third bonding pad may provide an electrical pathway between devices on the first substrate and devices on the second substrate.

Abstract translation: 引入半导体器件和制造方法。 在一个实施例中，在第一衬底上形成一个或多个钝化层。 在钝化层中形成凹部，并且在凹部中形成第一接合焊盘，第二接合焊盘和第一通孔。 在一些实施例中，第一通孔可以与第一接合焊盘电接触并且可以提供到第一多个金属化层的电路径。 第一基板中的第一接合焊盘和第二接合焊盘与第三接合焊盘和第二接合焊盘对准，并且可以使用直接接合方法接合。 第一接合焊盘和第三接合焊盘之间的接合可以在第一基板上的设备和第二基板上的设备之间提供电路径。

公开(公告)号：US20150279816A1

公开(公告)日：2015-10-01

申请号：US14229114

申请日：2014-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Szu-Ying Chen ,  Dun-Nian Yaung

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L24/89 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0382 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/09515 ,  H01L2224/09517 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/8034 ,  H01L2224/80357 ,  H01L2224/8036 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/80001

Abstract: A semiconductor device, and a method of fabrication, is introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and a first bonding pad, a second bonding pad, and a first via are formed in the recesses. In some embodiment, the first via may have electrical contact with the first bonding pad and may provide an electrical pathway to a first plurality of metallization layers. The first bonding pad and the second bonding pad in the first substrate are aligned to a third bonding pad and the fourth bonding pad in a second substrate and may be bonded using a direct bonding method. A bond between the first bonding pad and the third bonding pad may provide an electrical pathway between devices on the first substrate and devices on the second substrate.

Abstract translation: 引入半导体器件和制造方法。 在一个实施例中，在第一衬底上形成一个或多个钝化层。 在钝化层中形成凹部，并且在凹部中形成第一接合焊盘，第二接合焊盘和第一通孔。 在一些实施例中，第一通孔可以与第一接合焊盘电接触并且可以提供到第一多个金属化层的电路径。 第一基板中的第一接合焊盘和第二接合焊盘与第三接合焊盘和第二接合焊盘对准，并且可以使用直接接合方法接合。 第一接合焊盘和第三接合焊盘之间的接合可以在第一基板上的设备和第二基板上的设备之间提供电路径。