公开(公告)号：US20170345806A1

公开(公告)日：2017-11-30

申请号：US15678586

申请日：2017-08-16

Applicant: OLYMPUS CORPORATION

Inventor： Yoshiaki Takemoto

IPC: H01L25/18 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/321

CPC classification number: H01L25/18 ,  H01L21/3212 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L27/146 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14645 ,  H01L2224/05547 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80203 ,  H01L2224/8085 ,  H01L2224/80862 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2225/06513 ,  H01L2924/00014

Abstract: A semiconductor device includes a first substrate, an insulation layer, and a first electrode. The first substrate contains a first semiconductor material. The insulation layer includes a first surface, a second surface, and a third surface. The first electrode includes a fourth surface, a fifth surface, and a sixth surface, and contains a porous first conductive material. The second surface and the fifth surface configure the same surface. The third surface faces the sixth surface. A distance between the first surface and the first substrate is less than a distance between the second surface and the first substrate. A distance between the fourth surface and the first substrate is less than a distance between the fifth surface and the first substrate.

公开(公告)号：US09613930B2

公开(公告)日：2017-04-04

申请号：US14064093

申请日：2013-10-25

Applicant: Infineon Technologies AG

Inventor： Petteri Palm

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/29 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/89 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/24 ,  H01L24/31 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05018 ,  H01L2224/08112 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/80031 ,  H01L2224/80488 ,  H01L2224/80801 ,  H01L2224/8082 ,  H01L2224/8085 ,  H01L2224/80904 ,  H01L2224/8203 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/83851 ,  H01L2224/83889 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US11894335B2

公开(公告)日：2024-02-06

申请号：US17337626

申请日：2021-06-03

Applicant: Japan Display Inc.

Inventor： Kazuyuki Yamada ,  Keisuke Asada ,  Kenichi Takemasa

IPC: H01L33/62 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L25/167 ,  H01L33/62 ,  H01L24/05 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/08145 ,  H01L2224/08502 ,  H01L2224/80004 ,  H01L2224/80024 ,  H01L2224/8085 ,  H01L2224/80224 ,  H01L2224/80805 ,  H01L2224/80907 ,  H01L2924/12041 ,  H01L2924/1426

Abstract: A method for manufacturing a display device includes preparing a circuit board including a drive circuit for driving a LED chip, forming a connecting electrode on the circuit board, forming an adhesive layer on the connecting electrode, adhering a terminal electrode of the LED chip on the adhesive layer and joining the connecting electrode and the terminal electrode by irradiating a laser light. The adhesive layer may be formed only on a upper surface of the connecting electrode.

公开(公告)号：US09230938B2

公开(公告)日：2016-01-05

申请号：US14583693

申请日：2014-12-27

Applicant: Renesas Electronics Corporation

Inventor： Akio Hasebe ,  Naohiro Makihira ,  Bunji Yasumura ,  Mitsuyuki Kubo ,  Fumikazu Takei ,  Yoshinori Deguchi

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L25/18 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L24/89 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/08235 ,  H01L2224/1146 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/8036 ,  H01L2224/8085 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

公开(公告)号：US20150255411A1

公开(公告)日：2015-09-10

申请号：US14198509

申请日：2014-03-05

Applicant: Omkar G. Karhade ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur

Inventor： Omkar G. Karhade ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur

IPC: H01L23/00 ,  G06F1/16 ,  H01L23/36

CPC classification number: H01L24/09 ,  G06F1/1658 ,  G06F1/1686 ,  G06F1/1688 ,  G06F1/1694 ,  G06F1/1698 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0807 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80138 ,  H01L2224/8085 ,  H01L2224/80897 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83127 ,  H01L2224/83129 ,  H01L2224/83855 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed towards die-to-die bonding and associated integrated circuit (IC) package configurations. In one embodiment, a package assembly includes a package substrate having a solder resist layer disposed on a first side and a second side disposed opposite to the first side, a first die mounted on the first side and having an active side that is electrically coupled with the package substrate by one or more first die-level interconnects and a second die bonded with the active side of the first die using one or more second die-level interconnects, wherein at least a portion of the second die is disposed in a cavity that extends into the solder resist layer. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及芯片到芯片的结合和相关联的集成电路（IC）封装配置。 在一个实施例中，封装组件包括封装衬底，其具有设置在第一侧上的阻焊层和与第一侧相对设置的第二侧，安装在第一侧上的第一管芯，并且具有与 所述封装衬底通过一个或多个第一裸片级互连和使用一个或多个第二管芯级互连件与所述第一管芯的所述有源侧接合的第二管芯，其中所述第二管芯的至少一部分设置在腔中， 延伸到阻焊层中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08960899B2

公开(公告)日：2015-02-24

申请号：US13627574

申请日：2012-09-26

Applicant: Google Inc.

Inventor： James Etzkorn

IPC: G02C7/02 ,  H01L23/48 ,  H01L21/56 ,  G02C7/04 ,  H01L23/00

CPC classification number: G02C11/10 ,  A61B5/6821 ,  A61B2562/12 ,  B29D11/00048 ,  B29D11/00807 ,  G02C7/04 ,  G02C7/049 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/97 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/08225 ,  H01L2224/11312 ,  H01L2224/13109 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8012 ,  H01L2224/8085 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00 ,  H01L2224/83104 ,  H01L2224/05599 ,  H01L2924/013 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/00013 ,  H01L2924/20105 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A contact lens having a thin silicon chip integrated therein is provided along with methods for assembling the silicon chip within the contact lens. In an aspect, a method includes creating a plurality of lens contact pads on a lens substrate and creating a plurality of chip contact pads on a chip. The method further involves applying assembly bonding material to the each of the plurality of lens contact pads or chip contact pads, aligning the plurality of lens contact pads with the plurality of chip contact pads, bonding the chip to the lens substrate via the assembly bonding material using flip chip bonding, and forming a contact lens with the lens substrate.

公开(公告)号：US20180301609A1

公开(公告)日：2018-10-18

申请号：US16006857

申请日：2018-06-13

Applicant: Epistar Corporation ,  IMEC Taiwan Co.

Inventor： Guan Ru He ,  Jui-Hung Yeh ,  Kevin T. Y. Huang ,  Chih Chung Chen

IPC: H01L33/62 ,  H01L21/683 ,  H01L25/075 ,  H01L23/00 ,  H01L33/48 ,  H01L33/36 ,  H01L27/15

CPC classification number: H01L33/62 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/29 ,  H01L24/40 ,  H01L24/48 ,  H01L24/64 ,  H01L24/66 ,  H01L24/69 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0753 ,  H01L27/153 ,  H01L33/36 ,  H01L33/486 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/29194 ,  H01L2224/32 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/64 ,  H01L2224/73251 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/8085 ,  H01L2224/80862 ,  H01L2224/80874 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/89 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2933/0016 ,  H01L2933/0066 ,  H01L2224/45099 ,  H01L2224/69 ,  H01L2224/83 ,  H01L2224/08 ,  H01L2224/85 ,  H01L2224/84 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: LED chip packaging assembly that facilitates an integrated method for mounting LED chips as a group to be pre-wired to be electrically connected to each other through a pattern of extendable metal wiring lines is provided. LED chips which are electrically connected to each other through extendable metal wiring lines, replace pick and place mounting and the wire bonding processes of the LED chips, respectively. Wafer level MEMS technology is utilized to form parallel wiring lines suspended and connected to various contact pads. Bonding wires connecting the LED chips are made into horizontally arranged extendable metal wiring lines which can be in a spring shape, and allowing for expanding and contracting of the distance between the connected LED chips. A tape is further provided to be bonded to the LED chips, and extended in size to enlarge distance between the LED chips to exceed the one or more prearranged distances.

公开(公告)号：US20150348935A1

公开(公告)日：2015-12-03

申请号：US14665514

申请日：2015-03-23

Applicant: Shawn O'Rourke

Inventor： Shawn O'Rourke

IPC: H01L23/00 ,  H05K3/38 ,  H05K3/00

CPC classification number: H01L24/89 ,  C09J5/06 ,  C09J2203/326 ,  C09J2205/302 ,  C09J2469/00 ,  H01L21/6835 ,  H01L23/4985 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/6835 ,  H01L2224/80007 ,  H01L2224/80047 ,  H01L2224/8085 ,  H01L2224/80948 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K3/007 ,  H05K3/386 ,  H05K2203/016 ,  H05K2203/083 ,  H05K2203/085 ,  H05K2203/1105 ,  Y10T29/49156

Abstract: Method for temporarily attaching a substrates to a rigid carrier is described which includes forming a sacrificial layer of a thermally-decomposable polymer, e.g., poly(alkylene carbonate), and bonding the flexible substrate to the rigid carrier with the sacrificial layer positioned therebetween. Electronic components and/or circuits may then be fabricated or other semiconductor processing steps employed (e.g., backgrinding) on the attached substrate. Once fabrication is completed, the substrate may be detached from the rigid carrier by heating the assembly to decompose the sacrificial layer.

Abstract translation: 描述了将基板临时附接到刚性载体的方法，其包括形成可热分解的聚合物（例如聚（碳酸亚烷基酯））的牺牲层，并且将柔性基板结合到刚性载体上，牺牲层位于它们之间。 然后可以制造电子元件和/或电路或在所附接的衬底上采用其他半导体处理步骤（例如，背面研磨）。 一旦制造完成，可以通过加热组件来分解牺牲层，从而将基板从刚性载体上拆下。

公开(公告)号：US09133367B2

公开(公告)日：2015-09-15

申请号：US13279564

申请日：2011-10-24

Applicant: Kyoung Jin Ha ,  Baek Soung Park ,  Ji Ho Kim ,  Min Kyu Hwang ,  Kil Sung Lee

Inventor： Kyoung Jin Ha ,  Baek Soung Park ,  Ji Ho Kim ,  Min Kyu Hwang ,  Kil Sung Lee

IPC: C09J7/02 ,  C09J143/02 ,  C09J133/10 ,  C09J133/08 ,  C09J143/04 ,  H01L21/683 ,  C08F8/30 ,  C09J133/14

CPC classification number: C09J7/02 ,  C08F8/30 ,  C09J7/20 ,  C09J133/08 ,  C09J133/10 ,  C09J133/14 ,  C09J143/02 ,  C09J143/04 ,  C09J2201/36 ,  C09J2201/606 ,  C09J2201/61 ,  C09J2203/326 ,  C09J2433/00 ,  H01L21/6836 ,  H01L2221/68336 ,  H01L2224/8085 ,  H01L2224/80855 ,  H01L2224/8385 ,  H01L2224/83855 ,  Y10T428/2848 ,  Y10T428/31786 ,  C08F2220/1858 ,  C08F220/20 ,  C08F220/32 ,  C08F2220/325 ,  C08F230/02 ,  C08F220/06

Abstract: An optically clear adhesive, a dicing die bonding film, and a semiconductor device, the optically clear adhesive including a curing agent; and an acrylic copolymer, the acrylic copolymer including an alkyl group, a hydroxyl group, and at least one of a phosphate group and a silane group.

Abstract translation: 光学透明粘合剂，切割芯片接合膜和半导体器件，光学透明粘合剂包括固化剂; 和丙烯酸共聚物，所述丙烯酸共聚物包括烷基，羟基和磷酸酯基和硅烷基中的至少一个。

公开(公告)号：US20150212340A1

公开(公告)日：2015-07-30

申请号：US14678198

申请日：2015-04-03

Applicant: Google Inc.

Inventor： James Etzkorn

IPC: G02C11/00 ,  H01L23/31 ,  H01L21/768 ,  H01L23/528 ,  H01L21/56 ,  H01L23/00

CPC classification number: G02C11/10 ,  A61B5/6821 ,  A61B2562/12 ,  B29D11/00048 ,  B29D11/00807 ,  G02C7/04 ,  G02C7/049 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/97 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/08225 ,  H01L2224/11312 ,  H01L2224/13109 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8012 ,  H01L2224/8085 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00 ,  H01L2224/83104 ,  H01L2224/05599 ,  H01L2924/013 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/00013 ,  H01L2924/20105 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A contact lens having a thin silicon chip integrated therein is provided along with methods for assembling the silicon chip within the contact lens. In an aspect, a method includes creating a plurality of lens contact pads on a lens substrate and creating a plurality of chip contact pads on a chip. The method further involves applying assembly bonding material to the each of the plurality of lens contact pads or chip contact pads, aligning the plurality of lens contact pads with the plurality of chip contact pads, bonding the chip to the lens substrate via the assembly bonding material using flip chip bonding, and forming a contact lens with the lens substrate.

Abstract translation: 集成有薄硅芯片的隐形眼镜与隐形眼镜中的硅芯片的组装方法一起提供。 一方面，一种方法包括在透镜基板上形成多个透镜接触焊盘并在芯片上产生多个芯片接触焊盘。 该方法还包括将组装接合材料施加到多个透镜接触焊盘或芯片接触焊盘中的每一个上，将多个透镜接触焊盘与多个芯片接触焊盘对准，通过组装接合材料将芯片粘合到透镜基板 使用倒装芯片接合，并且与透镜基板形成隐形眼镜。