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公开(公告)号：US12108543B2
公开(公告)日：2024-10-01
申请号：US17689986
申请日：2022-03-09
发明人： Chiao-Pei Chen , Chun-Hsiung Chou
CPC分类号： H05K3/462 , G01R1/07307 , H05K1/0284 , H05K2203/016
摘要： A testing substrate includes a first build-up structure and a ceramic substrate. The ceramic substrate is arranged on the first build-up structure. The first bonding interface between the first build-up structure and the ceramic substrate includes a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface. A manufacturing method of a testing substrate and a probe card are also provided.
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公开(公告)号：US20240321762A1
公开(公告)日：2024-09-26
申请号：US18678813
申请日：2024-05-30
申请人： Intel Corporation
发明人： Mihir K. Roy , Stefanie M. Lotz , Wei-Lun Kane Jen
IPC分类号： H01L23/538 , H01L21/48 , H01L23/00 , H01L23/13 , H01L23/14 , H01L23/498 , H01L25/065 , H05K1/03 , H05K1/14 , H05K1/18 , H05K3/34 , H05K3/46
CPC分类号： H01L23/5386 , H01L21/4853 , H01L23/13 , H01L23/145 , H01L23/49811 , H01L23/49866 , H01L23/49894 , H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H05K1/141 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/81193 , H01L2224/81203 , H01L2924/0002 , H01L2924/0665 , H01L2924/12042 , H01L2924/15192 , H01L2924/1579 , H01L2924/2064 , H05K1/0313 , H05K1/142 , H05K1/181 , H05K3/3436 , H05K3/467 , H05K2201/048 , H05K2201/049 , H05K2201/10522 , H05K2201/10674 , H05K2203/016
摘要： Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.
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公开(公告)号：US12002762B2
公开(公告)日：2024-06-04
申请号：US16889190
申请日：2020-06-01
申请人： Intel Corporation
发明人： Mihir K Roy , Stefanie M Lotz , Wei-Lun Kane Jen
IPC分类号： H01L23/00 , H01L21/48 , H01L23/13 , H01L23/14 , H01L23/498 , H01L23/538 , H01L25/065 , H05K1/14 , H05K1/03 , H05K1/18 , H05K3/34 , H05K3/46
CPC分类号： H01L23/5386 , H01L21/4853 , H01L23/13 , H01L23/145 , H01L23/49811 , H01L23/49866 , H01L23/49894 , H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H05K1/141 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/81193 , H01L2224/81203 , H01L2924/0002 , H01L2924/0665 , H01L2924/12042 , H01L2924/15192 , H01L2924/1579 , H01L2924/2064 , H05K1/0313 , H05K1/142 , H05K1/181 , H05K3/3436 , H05K3/467 , H05K2201/048 , H05K2201/049 , H05K2201/10522 , H05K2201/10674 , H05K2203/016 , H01L2924/12042 , H01L2924/00
摘要： Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.
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公开(公告)号：US20180126607A1
公开(公告)日：2018-05-10
申请号：US15808371
申请日：2017-11-09
CPC分类号： B29C41/26 , B29C41/42 , B29C59/10 , B29C59/14 , B29C71/04 , B29C2035/0822 , B29C2035/0827 , B29K2083/00 , B29K2995/0062 , B29L2031/3425 , C08J3/247 , C08J5/18 , C08J7/04 , C08J2383/04 , D21H19/00 , D21H19/20 , D21H19/54 , D21H19/56 , D21H19/60 , D21H19/82 , H01B3/46 , H05K3/0055 , H05K3/007 , H05K2203/0143 , H05K2203/016
摘要： A method of producing a printed electronic device on a thin PDMS film which includes coupling a first layer of a water-soluble polymer to a substrate and drying the first layer of the water-soluble polymer. The method further includes coupling a second layer of a crosslinkable PDMS polymer to the first layer of the water-soluble polymer and curing the second layer of the crosslinkable PDMS polymer to form the thin PDMS film. The method also includes printing one or more functional layers on the thin PDMS film and drying the one or more functional layers on the thin PDMS film to form the printed electronic device coupled to the substrate.
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公开(公告)号：US09894775B2
公开(公告)日：2018-02-13
申请号：US14905115
申请日：2014-06-24
申请人： SONY CORPORATION
发明人： Shin Akasaka , Satoshi Kumon , Kentarou Satou , Yuki Oishi
CPC分类号： H05K3/26 , B24B37/042 , G06F1/16 , G06F1/1613 , H05K3/0044 , H05K3/0055 , H05K3/007 , H05K2203/016
摘要： There is provided a method of manufacturing a substrate, the method including: polishing a surface of a material substrate; and forming a penalization film on the surface of the material substrate alter the polishing of the surface of the material substrate.
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公开(公告)号：US20180019237A1
公开(公告)日：2018-01-18
申请号：US15714712
申请日：2017-09-25
发明人： Yoichiro KURITA , Masaya KAWANO , Koji SOEJIMA
IPC分类号： H01L25/00 , H01L21/56 , H01L23/00 , H01L25/18 , H01L21/683 , H01L23/538
CPC分类号： H01L25/50 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L23/3121 , H01L23/49816 , H01L23/522 , H01L23/5226 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/02 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2221/68345 , H01L2221/68372 , H01L2224/02319 , H01L2224/02331 , H01L2224/02333 , H01L2224/02372 , H01L2224/02373 , H01L2224/02379 , H01L2224/02381 , H01L2224/16137 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2225/06513 , H01L2225/06544 , H01L2225/06555 , H01L2225/06582 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/19105 , H05K3/0058 , H05K3/284 , H05K3/4682 , H05K2201/0195 , H05K2201/09527 , H05K2201/096 , H05K2201/09972 , H05K2203/016 , H05K2203/0733 , H05K2203/1469 , H01L2924/00 , H01L2224/0401
摘要： In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
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公开(公告)号：US09847325B2
公开(公告)日：2017-12-19
申请号：US15354484
申请日：2016-11-17
发明人： Yoichiro Kurita , Masaya Kawano , Koji Soejima
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/00 , H01L21/30 , H01L21/46 , H01L21/4763 , H01L25/00 , H01L21/56 , H01L21/683 , H01L25/18 , H01L23/538 , H01L23/00
CPC分类号： H01L25/50 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L23/3121 , H01L23/49816 , H01L23/522 , H01L23/5226 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/02 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2221/68345 , H01L2221/68372 , H01L2224/02319 , H01L2224/02331 , H01L2224/02333 , H01L2224/02372 , H01L2224/02373 , H01L2224/02379 , H01L2224/02381 , H01L2224/16137 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2225/06513 , H01L2225/06544 , H01L2225/06555 , H01L2225/06582 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/19105 , H05K3/0058 , H05K3/284 , H05K3/4682 , H05K2201/0195 , H05K2201/09527 , H05K2201/096 , H05K2201/09972 , H05K2203/016 , H05K2203/0733 , H05K2203/1469 , H01L2924/00 , H01L2224/0401
摘要： In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
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公开(公告)号：US09795037B2
公开(公告)日：2017-10-17
申请号：US14924020
申请日：2015-10-27
发明人： Koichi Sugitani , Hoon Kang , Chul Won Park , Yang-Ho Jung
CPC分类号： H05K3/06 , G06F3/0416 , G06F2203/04103 , H05K3/007 , H05K3/064 , H05K2201/0145 , H05K2201/026 , H05K2201/0323 , H05K2201/0326 , H05K2201/0329 , H05K2201/10128 , H05K2203/016
摘要： A touch panel includes: a uni-axially oriented base film; a transparent electrode pattern layer positioned on the uni-axially oriented base film; a first passivation layer formed in an edge region of the transparent electrode pattern layer and covering end portion side walls of the transparent electrode pattern layer; and a contact hole positioned on the first passivation layer and exposing the first passivation layer.
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9.发明申请公开(公告)号：US20170207171A1
公开(公告)日：2017-07-20
申请号：US15323916
申请日：2015-10-19
发明人： Yong-Jin KIM , Jae-Hak LEE , Ju-Yong LEE , Joon-Yub SONG , Seung-Man KIM , Chang-Woo LEE , Tae-Ho HA
IPC分类号： H01L23/538 , H01L23/498 , H01L21/48 , H01L23/14
CPC分类号： H05K3/0017 , H01L21/027 , H01L21/304 , H01L21/486 , H01L21/768 , H01L23/145 , H01L23/49866 , H01L23/5384 , H01L23/5387 , H05K1/0326 , H05K1/0346 , H05K1/113 , H05K1/118 , H05K3/007 , H05K3/423 , H05K2201/0154 , H05K2201/09563 , H05K2203/016
摘要： In a flexible substrate and a method for manufacturing the flexible substrate, the flexible substrate includes a polymer substrate, a through conductive material, an upper conductive material and a lower conductive material. The polymer substrate has a via-hole, and the via-hole is formed by a pattern formed via a photolithography and passes through the polymer substrate. The through conductive material fills the via-hole of the polymer substrate. The upper conductive material is planarized and is patterned to form an upper substrate of the polymer substrate in a plane with an upper substrate of the through conductive material. The lower conductive material is planarized and is patterned to form a lower substrate of the polymer substrate in a plane with a lower substrate of the through conductive material.
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公开(公告)号：US20170169918A1
公开(公告)日：2017-06-15
申请号：US15220866
申请日：2016-07-27
发明人： Chan Woo PARK , Jae Bon KOO , Bock Soon NA , Rae-Man PARK , Ji-Young OH , Sang Seok LEE , Soon-Won JUNG
IPC分类号： H01B7/06 , H01B13/008
CPC分类号： H01B7/06 , H01B13/008 , H05K1/0283 , H05K3/007 , H05K3/107 , H05K3/20 , H05K2201/0329 , H05K2201/0338 , H05K2201/035 , H05K2203/016 , H05K2203/0568 , H05K2203/128
摘要： Provided is a stretchable wire including: a stretchable solid-phase conductive structure; a stretchable insulation layer which surrounds the solid-phase conductive structure; and a liquid-phase conductive material layer disposed between the solid-phase conductive structure and the stretchable insulation layer, and in contact with the solid-phase conductive structure, and a method of fabricating the same.
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