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    High density interconnect device and method
    1.
    发明授权
    High density interconnect device and method 有权

    公开(公告)号：US11158578B2

    公开(公告)日：2021-10-26

    申请号：US16601297

    申请日：2019-10-14

    Applicant: Intel Corporation

    Inventor： Mihir K Roy ,  Mathew J Manusharow

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/14 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L25/065 ,  H01L25/18

    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

    High density interconnect device and method
    3.
    发明授权
    High density interconnect device and method 有权

    公开(公告)号：US10446499B2

    公开(公告)日：2019-10-15

    申请号：US15438321

    申请日：2017-02-21

    Applicant: Intel Corporation

    Inventor： Mihir K Roy ,  Mathew J Manusharow

    IPC: H01L23/13 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

    Method of making an inductor
    6.
    发明授权
    Method of making an inductor 有权

    公开(公告)号：US10998120B2

    公开(公告)日：2021-05-04

    申请号：US16162465

    申请日：2018-10-17

    Applicant: Intel Corporation

    Inventor： William J. Lambert ,  Mihir K Roy ,  Mathew J Manusharow ,  Yikang Deng

    IPC: H01F7/06 ,  H01F27/28 ,  H01F17/00 ,  H01F41/04 ,  C25D5/16 ,  C25D5/48 ,  C25D7/00 ,  H01F27/255 ,  H01F41/02

    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

    High density organic bridge device and method
    8.
    发明授权
    High density organic bridge device and method 有权

    公开(公告)号：US10103105B2

    公开(公告)日：2018-10-16

    申请号：US15350393

    申请日：2016-11-14

    Applicant: Intel Corporation

    Inventor： Mihir K Roy ,  Stefanie M Lotz ,  Wei-Lun Kane Jen

    IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065 ,  H01L21/683 ,  H01L23/00

    Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

    Electrical interconnect formed through buildup process
    9.
    发明授权
    Electrical interconnect formed through buildup process 有权

    公开(公告)号：US10028394B2

    公开(公告)日：2018-07-17

    申请号：US13717048

    申请日：2012-12-17

    Applicant: Intel Corporation

    Inventor： Mihir K Roy ,  Matthew J Manusharow

    IPC: H05K3/46 ,  H05K3/40 ,  H01L23/498 ,  H01L21/48 ,  H05K3/10 ,  H01L23/538 ,  H05K1/18

    Abstract: This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.

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