公开(公告)号：US12094831B2

公开(公告)日：2024-09-17

申请号：US18301700

申请日：2023-04-17

申请人： Tahoe Research, Ltd.

发明人： Mihir K. Roy ,  Mathew J. Manusharow

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/14 ,  H01L24/17 ,  H01L24/25 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L23/147 ,  H01L24/13 ,  H01L2224/13101 ,  H01L2224/1412 ,  H01L2224/14505 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/24146 ,  H01L2224/2541 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/381 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81203 ,  H01L2924/00014 ,  H01L2224/81986 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/00

摘要： Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

公开(公告)号：US20240055420A1

公开(公告)日：2024-02-15

申请号：US18169295

申请日：2023-02-15

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Kaimin LV ,  LING-YI CHUANG

IPC分类号： H01L25/18 ,  H10B80/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/482 ,  H01L23/00

CPC分类号： H01L25/18 ,  H10B80/00 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/482 ,  H01L24/11 ,  H01L24/14 ,  H01L2924/1436 ,  H01L2224/1412

摘要： A semiconductor package structure includes: a first base plate; a first semiconductor chip connected to the first base plate; a second semiconductor chip stacking structure including at least one first chip stacking structure and at least one second chip stacking structure; and a plurality of second base plates. The first and second chip stacking structures are arranged side-by-side on the first semiconductor chip in a first direction, a plurality of second conductive bumps are formed on sides of the first and second chip stacking structure that is away from each other in the first direction, the first direction being parallel to a plane where the first base plate is located. A signal line in each second base plate is connected to the second conductive bumps. The second base plates are connected to the first base plate in a direction perpendicular to the plane where the first base plate is located.

公开(公告)号：US20230253337A1

公开(公告)日：2023-08-10

申请号：US18301700

申请日：2023-04-17

申请人： Tahoe Research, Ltd.

发明人： Mihir K. ROY ,  Mathew J. MANUSHAROW

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/5386 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L24/14 ,  H01L21/4857 ,  H01L23/13 ,  H01L24/25 ,  H01L21/4853 ,  H01L23/5383 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/16225 ,  H01L2224/1712 ,  H01L2224/1412 ,  H01L24/13 ,  H01L2224/13101 ,  H01L2224/14505 ,  H01L2224/81986 ,  H01L23/147

摘要： Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

公开(公告)号：US11682607B2

公开(公告)日：2023-06-20

申请号：US17164729

申请日：2021-02-01

申请人： QUALCOMM Incorporated

发明人： Hong Bok We ,  Marcus Hsu ,  Aniket Patil

IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/14051

摘要： A package that includes a substrate and an integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first material, and a plurality of surface interconnects coupled to the plurality of interconnects. The plurality of surface interconnects comprises a second material. A surface of the plurality of surface interconnects is planar with a surface of the substrate. The integrated device is coupled to the plurality of surface interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects.

公开(公告)号：US20180331036A1

公开(公告)日：2018-11-15

申请号：US15773950

申请日：2015-12-26

申请人： Intel Corporation

发明人： Yu Amos ZHANG ,  Gabriel S. REGALADO ,  Zhiguo QIAN ,  Kemal AYGUN

IPC分类号： H01L23/528 ,  H01L23/66 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H01L23/00 ,  H01R13/6471

CPC分类号： H01L23/5286 ,  H01L21/4857 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/17 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01R13/6471 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0243

摘要： A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical, isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.

公开(公告)号：US20180076105A1

公开(公告)日：2018-03-15

申请号：US15641288

申请日：2017-07-04

申请人： Samsung Electronics Co., Ltd.

发明人： Baek KI ,  Tark-Hyun KO ,  Kun-Dae YEOM ,  Yong-Kwan LEE ,  Keun-Ho JANG

IPC分类号： H01L23/10 ,  H01L23/057 ,  H01L23/00

CPC分类号： H01L23/10 ,  H01L21/561 ,  H01L21/565 ,  H01L23/057 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2924/00014

摘要： A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.

公开(公告)号：US20180053741A1

公开(公告)日：2018-02-22

申请号：US15803008

申请日：2017-11-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC分类号： H01L23/00 ,  H01L25/00

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  H01L2924/384 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining a recess that is at least partially filled by the solder layer during reflowing of the solder layer.

公开(公告)号：US20170352631A1

公开(公告)日：2017-12-07

申请号：US15281095

申请日：2016-09-30

申请人： ChipMOS Technologies Inc.

发明人： Kun-Shu Chuang

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/02 ,  H01L23/3192 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/02145 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02373 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1412 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/014

摘要： Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump. The pad is disposed on the substrate. The protective layer is disposed on the substrate. The protective layer has a first opening exposing a portion of a surface of the pad. The convex patterns are disposed on the protective layer. The RDL is disposed on the convex patterns. The RDL extends from the pad to the convex patterns. The bump is disposed on the convex patterns.

公开(公告)号：US09659926B2

公开(公告)日：2017-05-23

申请号：US15200246

申请日：2016-07-01

申请人： Renesas Electronics Corporation

发明人： Shinya Suzuki ,  Kiichi Makuta

IPC分类号： H01L27/02 ,  G02F1/1345 ,  H01L23/00 ,  H01L23/498 ,  G02F1/133 ,  H01L23/532

CPC分类号： H01L24/17 ,  G02F1/13306 ,  G02F1/13452 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0292 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13644 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/9211 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.

公开(公告)号：US20160372447A1

公开(公告)日：2016-12-22

申请号：US15250951

申请日：2016-08-30

申请人： Samsung Electronics Co., Ltd.

发明人： Hye-young JANG ,  Chang-Seong JEON ,  CHAJEA JO ,  Taeje CHO

IPC分类号： H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/1412 ,  H01L2224/1413 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17104 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/321 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83379 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

摘要： A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.