Patent search cpc:"H01L2224/14153" Page 1

1.

发明授权
Method of forming bump structure having a side recess and semiconductor structure including the same 有权
Title translation: 形成具有侧凹部的凸块结构的方法和包括其的半导体结构

公开(公告)号：US09520379B2

公开(公告)日：2016-12-13

申请号：US15057302

申请日：2016-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen , Yen-Liang Lin

IPC: H01L23/00 , H01L25/00

CPC classification number: H01L24/16 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/81 , H01L25/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05572 , H01L2224/05599 , H01L2224/10145 , H01L2224/11849 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13018 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/14051 , H01L2224/1412 , H01L2224/14152 , H01L2224/14153 , H01L2224/16238 , H01L2224/81191 , H01L2224/81345 , H01L2224/81815 , H01L2924/00014 , H01L2924/01322 , H01L2924/2064 , Y10T428/12493 , Y10T428/24479 , H01L2924/014 , H01L2924/00012 , H01L2924/00

Abstract: In some embodiments, the present invention relates to a method of integrated chip bonding. The method forms a conductive trace on a surface of a first work piece, and a conductive bump on a surface of a second work piece. The conductive bump has a recess. A reflow process is performed on a solder layer to electrically couple the conductive trace and the conductive bump. The solder layer fills a part of the recess during the reflow process. By filling the recess during the reflow process, electrical shorting between the conductive trace and an adjacent conductive is reduced.

Abstract translation: 在一些实施例中，本发明涉及集成芯片接合的方法。该方法在第一工件的表面上形成导电迹线，并在第二工件的表面上形成导电凸块。导电凸块具有凹部。在焊料层上进行回流处理，以电耦合导电迹线和导电凸块。在回流过程中，焊料层填充凹部的一部分。通过在回流工艺期间填充凹槽，导电迹线和相邻导电体之间的电短路减小。

2.

发明授权
Semiconductor device and a method of manufacturing the same 有权

公开(公告)号：US09484287B2

公开(公告)日：2016-11-01

申请号：US14953390

申请日：2015-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinya Suzuki

IPC: H01L23/485 , H01L23/528 , H01L21/768 , H01L23/522 , H01L23/00 , G02F1/1345 , H01L21/02 , H01L21/3105 , H01L21/311 , H01L27/13 , H01L29/78

CPC classification number: H01L24/14 , G02F1/13306 , G02F1/133345 , G02F1/134309 , G02F1/13439 , G02F1/1345 , G02F1/13458 , G02F1/136286 , G02F1/1368 , G02F2001/133302 , H01L21/02164 , H01L21/0217 , H01L21/31055 , H01L21/31111 , H01L21/768 , H01L21/76819 , H01L23/485 , H01L23/522 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/81 , H01L24/83 , H01L27/13 , H01L29/7833 , H01L2224/02122 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05073 , H01L2224/05075 , H01L2224/051 , H01L2224/05144 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05184 , H01L2224/05553 , H01L2224/056 , H01L2224/1146 , H01L2224/1147 , H01L2224/13005 , H01L2224/13006 , H01L2224/13009 , H01L2224/13013 , H01L2224/13022 , H01L2224/13027 , H01L2224/13144 , H01L2224/14153 , H01L2224/16225 , H01L2224/271 , H01L2224/2929 , H01L2224/29355 , H01L2224/29444 , H01L2224/32225 , H01L2224/81 , H01L2224/81191 , H01L2224/8185 , H01L2224/83101 , H01L2224/83203 , H01L2224/83851 , H01L2224/9211 , H01L2224/93 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/04941 , H01L2924/05042 , H01L2924/05442 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1426 , H01L2924/15788 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2224/11 , H01L2224/83 , H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

3.

发明授权
Semiconductor device and a method of manufacturing the same 有权

公开(公告)号：US09484286B2

公开(公告)日：2016-11-01

申请号：US14953382

申请日：2015-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinya Suzuki

IPC: H01L23/485 , H01L23/528 , H01L21/768 , H01L23/522 , H01L23/00 , G02F1/1345 , H01L21/02 , H01L21/3105 , H01L21/311 , H01L27/13 , H01L29/78

CPC classification number: H01L24/14 , G02F1/13306 , G02F1/133345 , G02F1/134309 , G02F1/13439 , G02F1/1345 , G02F1/13458 , G02F1/136286 , G02F1/1368 , G02F2001/133302 , H01L21/02164 , H01L21/0217 , H01L21/31055 , H01L21/31111 , H01L21/768 , H01L21/76819 , H01L23/485 , H01L23/522 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/81 , H01L24/83 , H01L27/13 , H01L29/7833 , H01L2224/02122 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05073 , H01L2224/05075 , H01L2224/051 , H01L2224/05144 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05184 , H01L2224/05553 , H01L2224/056 , H01L2224/1146 , H01L2224/1147 , H01L2224/13005 , H01L2224/13006 , H01L2224/13009 , H01L2224/13013 , H01L2224/13022 , H01L2224/13027 , H01L2224/13144 , H01L2224/14153 , H01L2224/16225 , H01L2224/271 , H01L2224/2929 , H01L2224/29355 , H01L2224/29444 , H01L2224/32225 , H01L2224/81 , H01L2224/81191 , H01L2224/8185 , H01L2224/83101 , H01L2224/83203 , H01L2224/83851 , H01L2224/9211 , H01L2224/93 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/04941 , H01L2924/05042 , H01L2924/05442 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1426 , H01L2924/15788 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2224/11 , H01L2224/83 , H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

4.

发明授权
Contact test structure and method 有权

公开(公告)号：US09368417B2

公开(公告)日：2016-06-14

申请号：US14846614

申请日：2015-09-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen

IPC: H01L21/66 , H01L23/482 , H01L23/00

CPC classification number: H01L22/34 , H01L22/30 , H01L22/32 , H01L23/4824 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05008 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05569 , H01L2224/05572 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/0603 , H01L2224/06179 , H01L2224/06505 , H01L2224/11015 , H01L2224/13006 , H01L2224/13022 , H01L2224/13026 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14153 , H01L2224/14155 , H01L2924/01029 , H01L2924/00014 , H01L2924/207 , H01L2924/014

Abstract: A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

5.

发明申请
SEMICONDUCTOR DEVICE, SEMICONDUCTOR ELEMENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
Title translation: 半导体器件，半导体器件及制造半导体器件的方法

公开(公告)号：US20130134594A1

公开(公告)日：2013-05-30

申请号：US13680931

申请日：2012-11-19

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Yoshihiro Machida

IPC: H01L23/488 , H01L21/768

CPC classification number: H01L23/488 , H01L21/768 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2224/0346 , H01L2224/0401 , H01L2224/05554 , H01L2224/05571 , H01L2224/1146 , H01L2224/11472 , H01L2224/11474 , H01L2224/11831 , H01L2224/11906 , H01L2224/13012 , H01L2224/13014 , H01L2224/13018 , H01L2224/13076 , H01L2224/13083 , H01L2224/13147 , H01L2224/13166 , H01L2224/141 , H01L2224/14153 , H01L2224/14155 , H01L2224/16237 , H01L2224/81191 , H01L2224/81194 , H01L2224/81411 , H01L2224/81815 , H01L2224/94 , H01L2924/00014 , H01L2924/01022 , H01L2924/01074 , H01L2924/00012 , H01L2924/01047 , H01L2924/0103 , H01L2224/11

Abstract: A semiconductor device includes a semiconductor element on which electrode pads are laid out. A wiring substrate includes connecting pads respectively arranged in correspondence with the electrode pads. Pillar-shaped electrode terminals are respectively formed on the electrode pads of the semiconductor element. A solder joint electrically connects a distal portion of each electrode terminal and the corresponding connecting pad on the wiring substrate. Each electrode terminal includes a basal portion, which is connected to the corresponding electrode pad, and a guide, which is formed in the distal portion. The guide has a smaller cross-sectional area than the basal portion as viewed from above. The guide has a circumference and the basal portion has a circumference that is partially flush with the circumference of the guide. The guide is formed to guide solder toward the circumference of the guide.

Abstract translation: 半导体器件包括布置有电极焊盘的半导体元件。布线基板包括分别布置成与电极焊盘相对应的连接焊盘。柱状电极端子分别形成在半导体元件的电极焊盘上。焊接点电连接每个电极端子的远端部分和布线基板上的对应的连接焊盘。每个电极端子包括连接到相应的电极焊盘的基部和形成在远端部分中的引导件。如上所述，导向件具有比基部更小的横截面面积。引导件具有圆周，并且基部具有与引导件的圆周部分齐平的圆周。引导件被形成以引导焊料朝向引导件的圆周。

6.

发明申请
SEMICONDUCTOR CHIP AND MOUNTING STRUCTURE OF THE SAME (as amended) 审中-公开
Title translation: 半导体芯片及其安装结构（经修订）

公开(公告)号：US20120080789A1

公开(公告)日：2012-04-05

申请号：US13377780

申请日：2010-02-02

Applicant: Motoji Shiota , Hiroki Nakahama , Takashi Matsui , Takeshi Horiguchi

Inventor： Motoji Shiota , Hiroki Nakahama , Takashi Matsui , Takeshi Horiguchi

IPC: H01L23/498

CPC classification number: H01L24/14 , H01L21/563 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/13013 , H01L2224/1403 , H01L2224/14131 , H01L2224/14133 , H01L2224/14135 , H01L2224/14136 , H01L2224/14151 , H01L2224/14152 , H01L2224/14153 , H01L2224/14155 , H01L2224/14156 , H01L2224/14177 , H01L2224/16225 , H01L2224/17517 , H01L2224/26145 , H01L2224/2929 , H01L2224/29299 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81903 , H01L2224/83101 , H01L2224/83192 , H01L2224/83203 , H01L2224/83851 , H01L2224/9211 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/0665 , H01L2924/0781 , H01L2924/14 , H01L2924/15788 , H01L2924/381 , H01L2924/00 , H01L2224/29099 , H01L2224/29199 , H01L2224/13099 , H01L2224/81 , H01L2224/83

Abstract: Provided is a semiconductor chip having a narrowed pitch between terminals, the chip being capable of suppressing occurrence of poor connection between the chip and a substrate on which the chip is mounted. In an LSI chip including an input bump group, which is composed of a plurality of input bumps aligned in a line along one long side of its bottom surface, and an output bump group, which is composed of a plurality of output bumps arranged in a staggered manner along the other long side of the bottom surface, a dummy bump group is provided in an area between an area where the input bump group is provided and an area where the output bump group is provided, the dummy bump group including a plurality of rectangular dummy bumps which have long side extending along a direction perpendicular to the long sides of the bottom surface.

Abstract translation: 提供了一种在端子之间具有窄间距的半导体芯片，该芯片能够抑制芯片与其上安装芯片的基板之间的连接不良的发生。在包括输入凸块组的LSI芯片中，所述输入凸块组由沿其底面的一个长边排列的多个输入凸块和输出凸块组组成，所述输出凸块组由多个输出凸块组成，沿着底面的另一长边交错排列，在设置有输入凸块组的区域和设置有输出凸块组的区域之间的区域中设置有虚设凸块组，该虚设凸块组包括多个具有沿着与底面的长边垂直的方向延伸的长边的矩形伪凸块。

7.

发明授权
Method of making lithographic contact springs 有权
Title translation: 制作平版印刷接触弹簧的方法

公开(公告)号：US06616966B2

公开(公告)日：2003-09-09

申请号：US09795024

申请日：2001-02-26

Applicant: Gaetan L. Mathieu , Benjamin N. Eldridge , Gary W. Grube

Inventor： Gaetan L. Mathieu , Benjamin N. Eldridge , Gary W. Grube

IPC: B05D512

CPC classification number: G01R1/06727 , C25D1/003 , G01R1/06733 , G01R1/06761 , G01R3/00 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/72 , H01L25/0657 , H01L2224/05166 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/111 , H01L2224/11334 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13019 , H01L2224/1308 , H01L2224/13099 , H01L2224/13599 , H01L2224/1403 , H01L2224/14051 , H01L2224/14133 , H01L2224/14136 , H01L2224/14153 , H01L2224/14155 , H01L2225/06513 , H01L2225/06527 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01045 , H01L2924/01046 , H01L2924/01055 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15787 , H01L2924/19041 , H01L2924/30105 , H05K3/326 , H05K3/4092 , Y10T29/49147 , H01L2924/00 , H01L2924/00014

Abstract: A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and removing a first portion of the masking material. In this embodiment, at least a portion of the first portion of the spring structure is freed of masking material. In one aspect of the invention, the method includes planarizing the masking material layer and structure material to remove a portion of the structure material. In another aspect, the spring structure formed includes one of a post portion, a beam portion, and a tip structure portion.

Abstract translation: 通过光刻技术形成包括弹簧接触元件的互连的方法。在一个实施例中，该方法包括在衬底的第一部分上施加掩模材料，掩模材料具有将限定弹簧结构的第一部分的开口，在开口中沉积结构材料（例如导电材料）并用结构材料过度填充开口，去除结构材料的一部分，以及去除掩模材料的第一部分。在该实施例中，弹簧结构的第一部分的至少一部分没有掩蔽材料。在本发明的一个方面，该方法包括平坦化掩模材料层和结构材料以去除结构材料的一部分。另一方面，形成的弹簧结构包括柱部分，梁部分和尖端结构部分中的一个。

8.

发明授权
Method of making and using lithographic contact springs 有权
Title translation: 制作和使用平版印刷接触弹簧的方法

公开(公告)号：US06268015B1

公开(公告)日：2001-07-31

申请号：US09205022

申请日：1998-12-02

Applicant: Gaetan L. Mathieu , Benjamin N. Eldridge , Gary W. Grube

Inventor： Gaetan L. Mathieu , Benjamin N. Eldridge , Gary W. Grube

IPC: B05D512

CPC classification number: G01R1/06727 , C25D1/003 , G01R1/06733 , G01R1/06761 , G01R3/00 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/72 , H01L25/0657 , H01L2224/05166 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/111 , H01L2224/11334 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13019 , H01L2224/1308 , H01L2224/13099 , H01L2224/13599 , H01L2224/1403 , H01L2224/14051 , H01L2224/14133 , H01L2224/14136 , H01L2224/14153 , H01L2224/14155 , H01L2225/06513 , H01L2225/06527 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01045 , H01L2924/01046 , H01L2924/01055 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15787 , H01L2924/19041 , H01L2924/30105 , H05K3/326 , H05K3/4092 , Y10T29/49147 , H01L2924/00 , H01L2924/00014

Abstract: A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and removing a first portion of the masking material. In this embodiment, at least a portion of the first portion of the spring structure is freed of masking material. In one aspect of the invention, the method includes planarizing the masking material layer and structure material to remove a portion of the structure material. In another aspect, the spring structure formed includes one of a post portion, a beam portion, and a tip structure portion.

Abstract translation: 通过光刻技术形成包括弹簧接触元件的互连的方法。在一个实施例中，该方法包括在衬底的第一部分上施加掩模材料，掩模材料具有将限定弹簧结构的第一部分的开口，在开口中沉积结构材料（例如导电材料）并用结构材料过度填充开口，去除结构材料的一部分，以及去除掩模材料的第一部分。在该实施例中，弹簧结构的第一部分的至少一部分没有掩蔽材料。在本发明的一个方面中，该方法包括平坦化掩模材料层和结构材料以去除结构材料的一部分。另一方面，形成的弹簧结构包括柱部分，梁部分和尖端结构部分中的一个。