公开(公告)号：US09748191B2

公开(公告)日：2017-08-29

申请号：US15264588

申请日：2016-09-13

Applicant: Renesas Electronics Corporation

Inventor： Shinya Suzuki

IPC: H01L23/485 ,  H01L23/498 ,  H01L23/52 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  G02F1/1345 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/13 ,  G02F1/133 ,  G02F1/1333 ,  G02F1/1343 ,  H01L29/78 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

公开(公告)号：US20160079202A1

公开(公告)日：2016-03-17

申请号：US14953382

申请日：2015-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinya Suzuki

IPC: H01L23/00 ,  G02F1/1345

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

公开(公告)号：US20140312493A1

公开(公告)日：2014-10-23

申请号：US14320686

申请日：2014-07-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinya Suzuki

IPC: H01L23/00 ,  H01L23/485

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surf ace protection film formed to cover the top wiring layer is flattened by CMP.

Abstract translation: 一种提高半导体芯片的凸块电极与安装基板的配线之间的耦合可靠性的技术，更具体地说，即使在布线位于突起电极下方的顶部布线层中时也能保证凸块电极的平坦度的技术，由此 提高凸起电极和形成在玻璃基板上的布线之间的耦合的可靠性。 在突起电极的非重叠区域下方的顶部布线层中形成由电力线或信号线构成的布线和虚设图案。 虚拟图案位于填充布线之间的空间以减少由布线引起的不规则和顶部布线层中的空间。 形成为覆盖顶部布线层的冲浪保护膜被CMP平坦化。

公开(公告)号：US20100171097A1

公开(公告)日：2010-07-08

申请号：US12651633

申请日：2010-01-04

Applicant: Youichi NAGAI ,  Hiroshi INADA

Inventor： Youichi NAGAI ,  Hiroshi INADA

IPC: H01L31/0352 ,  H01L31/18

CPC classification number: H01L27/14683 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2224/02122 ,  H01L2224/0401 ,  H01L2224/06179 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/1184 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/14515 ,  H01L2224/16148 ,  H01L2224/27334 ,  H01L2224/2745 ,  H01L2224/2747 ,  H01L2224/2761 ,  H01L2224/27622 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/81007 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/819 ,  H01L2224/83203 ,  H01L2224/839 ,  H01L2224/92 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/12036 ,  H01L2924/12043 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A method for manufacturing a detection device includes the steps of providing bonding bumps on at least one of a light-receiving element array and a read-out circuit multiplexer, fixing a bump height adjusting member for adjusting the heights of the bumps to the light-receiving element array and/or the read-out circuit multiplexer on which the bumps are provided, and pressing a flat plate on the tops of the bumps and deforming the bumps until the flat plate comes in contact with the end of the bump height adjusting member.

Abstract translation: 一种检测装置的制造方法，包括以下步骤：在受光元件阵列和读出电路多路复用器中的至少一个上设置接合凸块，固定凸起高度调节构件，用于将凸块的高度调节到发光元件阵列， 接收元件阵列和/或其上设置有凸块的读出电路多路复用器，并且在凸块的顶部上按压平板并使凸起变形，直到平板与凸块高度调节构件的端部接触 。

公开(公告)号：US06633087B2

公开(公告)日：2003-10-14

申请号：US09818455

申请日：2001-03-27

Applicant: Ming-Dou Ker ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC: H01L2940

CPC classification number: H01L24/05 ,  H01L23/5222 ,  H01L24/48 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

Abstract translation: 一种用于半导体器件的低电容焊盘。 在衬底中形成扩散区，并且在衬底上形成接合焊盘并与扩散区对准。 接合焊盘由堆叠的金属层和金属层制成。 堆叠的金属层由多个金属层和多个电介质层制成，并且金属层和电介质层交替堆叠。 堆叠在层叠金属层中的金属层形成有小面积。 堆叠在层叠金属层中的每个金属层通过插塞与相邻的金属层耦合

公开(公告)号：US06448641B2

公开(公告)日：2002-09-10

申请号：US09329648

申请日：1999-06-09

Applicant: Ming-Dou Ker ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC: H01L2312

CPC classification number: H01L24/05 ,  H01L23/5222 ,  H01L24/48 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

Abstract translation: 一种用于半导体器件的低电容焊盘。 在衬底中形成扩散区，并且在衬底上形成接合焊盘并与扩散区对准。 接合焊盘由堆叠的金属层和金属层制成。 堆叠的金属层由多个金属层和多个电介质层制成，并且金属层和电介质层交替堆叠。 堆叠在层叠金属层中的金属层形成有小面积。 堆叠在堆叠金属层中的每个金属层通过插塞与相邻的金属层耦合。

公开(公告)号：US20170005055A1

公开(公告)日：2017-01-05

申请号：US15264588

申请日：2016-09-13

Applicant: Renesas Electronics Corporation

Inventor： Shinya Suzuki

IPC: H01L23/00 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1345 ,  H01L23/528 ,  G02F1/133

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Abstract translation: 一种提高半导体芯片的凸块电极与安装基板的配线之间的耦合可靠性的技术，更具体地说，即使在布线位于突起电极下方的顶部布线层中时也能保证凸块电极的平坦度的技术，由此 提高凸起电极和形成在玻璃基板上的布线之间的耦合的可靠性。 在突起电极的非重叠区域下方的顶部布线层中形成由电力线或信号线构成的布线和虚设图案。 虚拟图案位于填充布线之间的空间以减少由布线引起的不规则和顶部布线层中的空间。 形成为覆盖顶部布线层的表面保护膜被CMP平坦化。

公开(公告)号：US09449837B2

公开(公告)日：2016-09-20

申请号：US14657354

申请日：2015-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai

IPC: H01L21/00 ,  H01L21/311 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/481 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/48 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02122 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/80001 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00014

Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.

Abstract translation: 本文公开了具有设置在第一半导体衬底上的第一再分布层（RDL）和设置在第二半导体衬底上的第二RDL的封装。 第一个RDL被绑定到第二个RDL。 封装还包括布置在第二RDL上并围绕第一RDL和第一半导体衬底的绝缘膜。 导电元件设置在第一RDL中。 通孔从绝缘膜的顶表面延伸穿过第一半导体衬底到导电元件，并且间隔物设置在第一半导体衬底和通孔之间。 间隔物延伸穿过第一半导体衬底。

公开(公告)号：US20160126264A1

公开(公告)日：2016-05-05

申请号：US14994016

申请日：2016-01-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinya SUZUKI

IPC: H01L27/13 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

公开(公告)号：US09236352B2

公开(公告)日：2016-01-12

申请号：US13334556

申请日：2011-12-22

Applicant: Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn ,  Dioscoro Merilo

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn ,  Dioscoro Merilo

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/48 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68336 ,  H01L2224/02122 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/48 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV.

Abstract translation: 半导体晶片具有多个半导体管芯。 围绕模具形成周边区域。 在周边区域形成绝缘材料。 绝缘材料的一部分被去除以形成通孔（THV）。 导电材料沉积在THV中以形成导电THV。 在导电THV和半导体管芯的接触焊盘之间形成导电层。 噪声吸收材料沉积在导电THV之间的周边区域中，以将半导体管芯与器件间干扰隔离。 噪声吸收材料从半导体管芯的第一侧延伸穿过周边区域到半导体管芯的第二侧。 噪声吸收材料具有角度，半圆形或矩形形状。 噪声吸收材料可以分散在导电THV之间的周边区域。