公开(公告)号：US09941240B2

公开(公告)日：2018-04-10

申请号：US13934982

申请日：2013-07-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Kai Liu ,  Chun-Lin Lu ,  Kai-Chiang Wu ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Yen-Ping Wang ,  Chia-Chun Miao

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/06152 ,  H01L2224/06179 ,  H01L2224/13005 ,  H01L2224/13028 ,  H01L2224/13116 ,  H01L2224/1403 ,  H01L2224/14152 ,  H01L2224/14179 ,  H01L2224/14515 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17104 ,  H01L2224/17515 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/00

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.

公开(公告)号：US20180033757A1

公开(公告)日：2018-02-01

申请号：US15720127

申请日：2017-09-29

Applicant: Renesas Electronics Corporation

Inventor： Akira YAJIMA

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05664 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14517 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01022 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2924/01073 ,  H01L2924/0496 ,  H01L2924/01046 ,  H01L2924/01044 ,  H01L2924/01078 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In the semiconductor device, a bump electrode which connects a semiconductor chip and a wiring board is made up of a first part surrounded by an insulating film and a second part exposed from the insulating film. Since it is possible to reduce a width of the bump electrode while increasing a height of the bump electrode, a distance between the neighboring bump electrodes can be increased, and a filling property of a sealing material can be improved.

公开(公告)号：US09818712B2

公开(公告)日：2017-11-14

申请号：US14596888

申请日：2015-01-14

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Paige M. Holm ,  Vijay Sarihan

IPC: H01L23/02 ,  H01L23/00

CPC classification number: H01L24/17 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06134 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/14134 ,  H01L2224/14179 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2224/03 ,  H01L2224/11

Abstract: A device package includes a substrate having an active surface. Electrical connection bumps are deposited on the active surface and are arranged in an array having a perimeter. At least one electronic component is formed at a region of the active surface, where the region is located outside of the perimeter of the array of electrical connection bumps. When the device package is coupled with external circuitry via the electrical connection bumps, the region at which the electronic component is formed is suspended over the electronic circuitry. This region is subject to a lower stress profile than a region of the active surface circumscribed by the perimeter. Thus, stress sensitive electronic components can be located in this lower stress region of the active surface.

公开(公告)号：US20170309588A1

公开(公告)日：2017-10-26

申请号：US15646721

申请日：2017-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chita Chuang ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/56 ,  H01L23/58 ,  H01L23/31 ,  H01L21/60

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/522 ,  H01L23/53238 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2021/60255 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14152 ,  H01L2224/14179 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/206 ,  H01L2924/00

Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.

公开(公告)号：US20170221860A1

公开(公告)日：2017-08-03

申请号：US15484056

申请日：2017-04-10

Applicant: ChipMOS Technologies Inc.

Inventor： Shih-Wen Chou

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3142 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/83

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

公开(公告)号：US20170141073A1

公开(公告)日：2017-05-18

申请号：US15419949

申请日：2017-01-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Chia-Chun Miao ,  Hung-Jen Lin

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03472 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0554 ,  H01L2224/05559 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/11015 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81148 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

公开(公告)号：US09653429B2

公开(公告)日：2017-05-16

申请号：US14855397

申请日：2015-09-16

Applicant: ChipMOS Technologies Inc. ,  ChipMOS Technologies (Bermuda) Ltd.

Inventor： Shih-Wen Chou

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3142 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/83

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

公开(公告)号：US09646954B2

公开(公告)日：2017-05-09

申请号：US13085745

申请日：2011-04-13

Applicant: Shih-Wei Liang ,  Yu-Wen Liu ,  Hsien-Wei Chen

Inventor： Shih-Wei Liang ,  Yu-Wen Liu ,  Hsien-Wei Chen

IPC: H01L23/58 ,  H01L29/10 ,  H01L25/065 ,  H01L21/66 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L22/34 ,  H01L23/522 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05572 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: An integrated circuit system comprising a first integrated and at least one of a second integrated circuit, interposer or printed circuit board. The first integrated circuit further comprising a wiring stack, bond pads electrically connected to the wiring stack, and bump balls formed on the bond pads. First portions of the wiring stack and the bond pads form a functional circuit, and second portions of the wiring stack and the bond pads form a test circuit. A portion of the bump balls comprising dummy bump balls. The dummy bump balls electrically connected to the second portions of the wiring stack and the bond pads. The at least one of the second integrated circuit, interposer or printed circuit board forming a portion of the test circuit.

公开(公告)号：US20160372436A1

公开(公告)日：2016-12-22

申请号：US15255963

申请日：2016-09-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung Wei Cheng ,  Tsung-Ding Wang ,  Chien-Hsun Lee

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/78 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L21/78 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0214 ,  H01L2224/0215 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05024 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06132 ,  H01L2224/06179 ,  H01L2224/06517 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14104 ,  H01L2224/14132 ,  H01L2224/14134 ,  H01L2224/14179 ,  H01L2224/14517 ,  H01L2224/16013 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17515 ,  H01L2224/17517 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

公开(公告)号：US20160148879A1

公开(公告)日：2016-05-26

申请号：US14821902

申请日：2015-08-10

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Karine Saxod ,  Marika Sorrieul

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/3171 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/1876 ,  H01L2224/1329 ,  H01L2224/13291 ,  H01L2224/14179 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/30135 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/81862 ,  H01L2224/81874 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is fixed to a front face of a support wafer. A protective wafer is located facing and at a distance from the front face of the chip, and an infused adhesive is interposed between the chip and the protective wafer and located on a zone of the front face of the chip outside a central region of this front face. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. An obstruction barrier is arranged between the chip and the protective wafer and is disposed outside the central region of the front face of the chip. An encapsulation ring surrounds the chip, the protective wafer and the obstruction barrier.

Abstract translation: 一种电子器件的制造方法和层叠结构的电子器件，其特征在于，包括固定在支撑晶片前面的集成电路芯片的背面。 保护晶片位于与芯片前表面相对并且距离芯片的前面一定距离处，并且输入的粘合剂被插入在芯片和保护晶片之间，并且位于该芯片的正面的中心区域外的区域 面对。 输注的粘合剂包括注入可固化粘合剂中的可固化粘合剂和固体间隔元件。 在芯片和保护晶片之间设置障碍屏障，并且设置在芯片前表面的中心区域的外侧。 封装环围绕芯片，保护晶片和阻塞屏障。