公开(公告)号：US11984415B2

公开(公告)日：2024-05-14

申请号：US17528954

申请日：2021-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yukyung Park ,  Ungcheon Kim ,  Wonil Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/544 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48

CPC classification number: H01L24/02 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L25/18 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/04 ,  H01L2223/54426 ,  H01L2224/0213 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03019 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/0603 ,  H01L2224/06182

Abstract: An interposer according to an embodiment of the present invention includes a base layer having opposite first and second surfaces, a wiring structure on the first surface of the base layer, an interposer protective layer disposed on the second surface of the base layer and having a pad recess with a lower surface of the interposer protective layer positioned at a first vertical level and a bottom surface of the pad recess positioned at a second vertical level that is higher than the first vertical level, an interposer pad of which a portion fills the pad recess of the interposer protective layer and the remaining portion protrudes from the interposer protective layer, and an interposer through electrode extending through the base layer and the interposer protective layer to the interposer pad, the interposer through electrode electrically connecting the wiring structure to the interposer pad.

公开(公告)号：US20240153900A1

公开(公告)日：2024-05-09

申请号：US18053290

申请日：2022-11-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHENG-FU HUANG ,  SHING-YIH SHIH

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/0215 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05663 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.

公开(公告)号：US09812414B1

公开(公告)日：2017-11-07

申请号：US15186100

申请日：2016-06-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L24/02 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02165 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/05096 ,  H01L2224/05548 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/06 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A chip package includes a first substrate; a first insulation layer disposed over the first substrate; a conductive structure disposed within the first insulation layer; a buffering member embedded into the first insulation layer; a redistribution layer (RDL) electrically connected with the conductive structure and disposed over the conductive structure and the buffering member; and a second insulation layer disposed over the RDL, wherein a portion of the RDL is exposed from the second insulation layer and disposed over the buffering member.

公开(公告)号：US09721916B2

公开(公告)日：2017-08-01

申请号：US15255963

申请日：2016-09-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung Wei Cheng ,  Tsung-Ding Wang ,  Chien-Hsun Lee

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/14 ,  H01L21/78 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0214 ,  H01L2224/0215 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05024 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06132 ,  H01L2224/06179 ,  H01L2224/06517 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14104 ,  H01L2224/14132 ,  H01L2224/14134 ,  H01L2224/14179 ,  H01L2224/14517 ,  H01L2224/16013 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17515 ,  H01L2224/17517 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

公开(公告)号：US09508668B2

公开(公告)日：2016-11-29

申请号：US14804617

申请日：2015-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Liang Lin ,  Yu-Jen Tseng ,  Chang-Chia Huang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.

Abstract translation: 凸块结构包括形成在衬底上的接触元件和覆盖衬底的钝化层。 钝化层包括暴露接触元件的钝化开口。 凸起结构还包括覆盖钝化层的聚酰亚胺层和电耦合到接触元件的凸块下金属（UBM）特征。 聚酰亚胺层具有暴露接触元件的聚酰亚胺开口，凸起下的金属特征具有UBM宽度。 凸起结构还包括在凸起下金属冶金特征上的铜柱。 铜柱的前端具有柱宽，UBM宽度大于柱宽。

公开(公告)号：US09368465B2

公开(公告)日：2016-06-14

申请号：US14514704

申请日：2014-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-Jae Park ,  Hyun-Suk Chun

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11916 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/07025 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: The method includes forming an upper layer on a lower layer, forming a metal interconnection in the upper layer, forming a passivation layer exposing a center part of the metal interconnection on the upper layer, forming a buffer pattern exposing the center part of the metal interconnection, and selectively and asymmetrically covering a peripheral region of the metal interconnect and a part of the passivation layer, forming a wrapping pattern covering the buffer pattern and exposing the center part of the metal interconnection on the passivation layer, and forming a pad pattern on the center part of the metal interconnection.

Abstract translation: 该方法包括在下层上形成上层，在上层形成金属互连，形成钝化层，暴露上层金属互连的中心部分，形成露出金属互连中心部分的缓冲图案 并且选择性地和不对称地覆盖金属互连的周边区域和钝化层的一部分，形成覆盖缓冲图案的包覆图案，并使钝化层上的金属互连的中心部分露出，并在 中心部分金属互连。

公开(公告)号：US09041113B2

公开(公告)日：2015-05-26

申请号：US13777951

申请日：2013-02-26

Applicant: LAPIS SEMICONDUCTOR CO., LTD.

Inventor： Chikashi Fuchigami

IPC: H01L27/02 ,  H01L29/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L27/027 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L29/78 ,  H01L2224/0215 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05078 ,  H01L2224/05124 ,  H01L2224/05187 ,  H01L2224/05551 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/10122 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/07025 ,  H01L2924/05442

Abstract: A semiconductor integrated device in which electrostatic discharge damage can be reliably prevented, includes a semiconductor substrate in which an electrostatic protection circuit including a second diffusion region surrounding a first diffusion region as a local region is formed in a main surface; a metal pad opposed to the main surface; and a conductive bump formed so as to face a top surface of the metal pad, wherein in a surface opposed to the metal pad of the conductive bump, a projection which is in contact with the metal pad is provided in a range opposed to the first diffusion region.

Abstract translation: 可以可靠地防止静电放电损坏的半导体集成器件包括：半导体衬底，其中在主表面上形成有包围作为局部区域的第一扩散区域的第二扩散区域的静电保护电路; 与主表面相对的金属垫; 以及形成为面对所述金属焊盘的顶面的导电性凸块，在与所述导电凸块的所述金属焊盘相对的表面中，与所述金属焊盘接触的突起设置在与所述第一 扩散区。

公开(公告)号：US20140144690A1

公开(公告)日：2014-05-29

申请号：US14090321

申请日：2013-11-26

Applicant: Commissariat A L'Energie Atomique et Aux Ene Alt

Inventor： Gabriel Pares

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/40

CPC classification number: H05K1/0296 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02123 ,  H01L2224/02141 ,  H01L2224/0215 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/036 ,  H01L2224/0381 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05584 ,  H01L2224/05644 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1148 ,  H01L2224/1181 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/16111 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/3201 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/00014 ,  H05K3/4084 ,  H05K3/467 ,  H01L2924/00015 ,  H01L2924/01047 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2224/051 ,  H01L2924/01074 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: The invention concerns the forming of a microelectronic device comprising a substrate containing at least one conductive pad, the said pad being provided with a bottom surface resting on the substrate and an upper surface opposite said bottom surface, the said upper surface of said pad having a stack applied thereto formed of a conductive layer and a protective dielectric layer comprising an opening called first opening facing said pad and exposing the said conductive layer, at least one insulating block (120a, 120b) being arranged on a peripheral region of said upper surface of said pad, the said insulating block (120a, 120b) having a cross-section forming a closed contour and comprising an opening called second opening, a conductive pillar (130a, 130b) being located in the centre of said contour in the said second opening.

Abstract translation: 本发明涉及形成微电子器件，其包括含有至少一个导电焊盘的衬底，所述衬垫设置有搁置在衬底上的底表面和与所述底表面相对的上表面，所述衬垫的所述上表面具有 叠层，其由导电层和保护电介质层构成，保护电介质层包括面向所述焊盘的第一开口的开口并暴露所述导电层，至少一个绝缘块（120a，120b）布置在所述上​​表面的外围区域 所述绝缘块（120a，120b）具有形成闭合轮廓的横截面并且包括称为第二开口的开口，导电柱（130a，130b）位于所述第二开口中的所述轮廓的中心 。

公开(公告)号：US20140077365A1

公开(公告)日：2014-03-20

申请号：US13904885

申请日：2013-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Liang Lin ,  Yu-Jen Tseng ,  Chang-Chia Huang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Abstract translation: 实施例的凸起结构包括形成在基底上的接触元件，覆盖在基底上的钝化层，钝化层具有暴露接触元件的钝化开口，覆盖钝化层的聚酰亚胺层，聚酰亚胺层具有暴露接触元件 电触点接触元件的凸起下金属（UMB）特征，具有UBM宽度的凸块下金属特征，以及在凸块下冶金特征上的铜柱，具有柱宽度的铜柱的远端，UBM 宽度大于柱宽。

公开(公告)号：US20120211900A1

公开(公告)日：2012-08-23

申请号：US13031546

申请日：2011-02-21

Applicant: DaeSik Choi ,  JoonYoung Choi ,  WonIl Kwon

Inventor： DaeSik Choi ,  JoonYoung Choi ,  WonIl Kwon

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/0519 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00

Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.

Abstract translation: 半导体晶片具有接触垫。 在晶片上形成第一绝缘层。 在第一绝缘层和接触垫上形成第二绝缘层。 去除第二绝缘层的一部分以露出接触垫。 第一UBM层形成在第二绝缘层和接触垫的轮廓之上并且跟随第二绝缘层和接触垫的轮廓以在接触垫上产生良好的孔。 在第一UBM层和接触垫上的阱中形成第一缓冲层。 在第一UBM层和第一缓冲层上形成第二UBM层。 在第二UBM层上形成第三UBM层。 在第三UBM层上形成凸块。 第一个缓冲层减少了凸块和接触垫上的应力。 可以在第二和第三UBM层之间形成第二缓冲层。