公开(公告)号：US09041113B2

公开(公告)日：2015-05-26

申请号：US13777951

申请日：2013-02-26

Applicant: LAPIS SEMICONDUCTOR CO., LTD.

Inventor： Chikashi Fuchigami

IPC: H01L27/02 ,  H01L29/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L27/027 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L29/78 ,  H01L2224/0215 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05078 ,  H01L2224/05124 ,  H01L2224/05187 ,  H01L2224/05551 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/10122 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/07025 ,  H01L2924/05442

Abstract: A semiconductor integrated device in which electrostatic discharge damage can be reliably prevented, includes a semiconductor substrate in which an electrostatic protection circuit including a second diffusion region surrounding a first diffusion region as a local region is formed in a main surface; a metal pad opposed to the main surface; and a conductive bump formed so as to face a top surface of the metal pad, wherein in a surface opposed to the metal pad of the conductive bump, a projection which is in contact with the metal pad is provided in a range opposed to the first diffusion region.

Abstract translation: 可以可靠地防止静电放电损坏的半导体集成器件包括：半导体衬底，其中在主表面上形成有包围作为局部区域的第一扩散区域的第二扩散区域的静电保护电路; 与主表面相对的金属垫; 以及形成为面对所述金属焊盘的顶面的导电性凸块，在与所述导电凸块的所述金属焊盘相对的表面中，与所述金属焊盘接触的突起设置在与所述第一 扩散区。

公开(公告)号：US10930638B2

公开(公告)日：2021-02-23

申请号：US16253227

申请日：2019-01-22

Applicant: LAPIS Semiconductor Co., Ltd.

Inventor： Chikashi Fuchigami

IPC: H01L27/02 ,  H01L27/06 ,  H01L23/52 ,  H01L23/60 ,  H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: The disclosure provides a semiconductor device that can reduce the area of the circuit elements formed thereon. The semiconductor device includes a first conductivity type region formed on a substrate and formed with a resistance element surrounded by an insulating film; a second conductivity type region laminated in contact with an upper surface of the resistance element; a capacitor formed on the resistance element via an interlayer insulating layer; a via electrically connecting a terminal of the resistance element and a terminal of the capacitor in series; and a power supply line and a ground line electrically connected to the other terminal of the resistance element and the other terminal of the capacitor respectively.

公开(公告)号：US20190229107A1

公开(公告)日：2019-07-25

申请号：US16253227

申请日：2019-01-22

Applicant: LAPIS Semiconductor Co., Ltd.

Inventor： Chikashi Fuchigami

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/64 ,  H01L23/60 ,  H01L23/528 ,  H01L27/06

Abstract: The disclosure provides a semiconductor device that can reduce the area of the circuit elements formed thereon. The semiconductor device includes a first conductivity type region formed on a substrate and formed with a resistance element surrounded by an insulating film; a second conductivity type region laminated in contact with an upper surface of the resistance element; a capacitor formed on the resistance element via an interlayer insulating layer; a via electrically connecting a terminal of the resistance element and a terminal of the capacitor in series; and a power supply line and a ground line electrically connected to the other terminal of the resistance element and the other terminal of the capacitor respectively.