公开(公告)号：US09892985B2

公开(公告)日：2018-02-13

申请号：US15212718

申请日：2016-07-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L23/147 ,  H01L23/3677 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/13013 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: One aspect of the present disclosure provides a semiconductor device. In some embodiments, the semiconductor device includes an integrated circuit die, at least one conductive terminal disposed on the integrated circuit die, a frame positioned on the integrated circuit die, wherein the frame substantially exposes the at least one conductive terminal, and at least one conductive bump positioned in the frame, wherein the at least one conductive bump electrically connects the at least one conductive terminal.

公开(公告)号：US09831155B2

公开(公告)日：2017-11-28

申请号：US15068206

申请日：2016-03-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/15311

Abstract: A chip package includes at least one integrated circuit die. The integrated circuit die includes a substrate portion having an internal plane between a front side and a back side, an electrical interconnect portion on the front side, a plurality of first connection terminals on an upper surface of the electrical interconnect portion, a plurality of second connection terminals on the back side of the substrate portion, a plurality of connection wirings electrically connecting the first connection terminals and the second connection terminals, a chip selection terminal between the internal plane of the substrate portion and the upper surface of the electrical interconnect portion, and a chip selection wiring connected to the chip selection terminal and one of the second connection terminals and the first connection terminals. At least one of the chip selection wiring and the plurality of connection wirings includes a tilted portion with respect to the back side of the substrate portion.

公开(公告)号：US10103114B2

公开(公告)日：2018-10-16

申请号：US15271748

申请日：2016-09-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

Abstract: A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

公开(公告)号：US09704818B1

公开(公告)日：2017-07-11

申请号：US15203055

申请日：2016-07-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0332 ,  H01L2224/03416 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05578 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/0569 ,  H01L2224/10126 ,  H01L2224/1112 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13011 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13078 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/1356 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13684 ,  H01L2224/1369 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor structure includes a substrate; a pad disposed over the substrate; a passivation disposed over the substrate and exposing a portion of the pad; and a bump disposed over the portion of the pad. The bump includes a buffering member disposed over the portion of the pad; and a conductive layer surrounding the buffering member and electrically connected to the pad.

公开(公告)号：US09761535B1

公开(公告)日：2017-09-12

申请号：US15194195

申请日：2016-06-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/18 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/18 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: One aspect of the present disclosure provides an interposer for a semiconductor package. The interposer includes a substrate portion and a wall portion disposed on the substrate portion. The substrate portion has a first side, a second side, and an electrical interconnect structure between the first side and the second side. The substrate portion is substantially free from conductive through vias, and the cost for fabricating through silicon vias (TSV) is very expensive; therefore, the fabrication cost of the interposer can be dramatically reduced. In addition, the wall portion is disposed on the first side and defining an aperture exposing a portion of the electrical interconnect structure. At least one semiconductor die can be bonded to the interposer and inside the aperture. Consequently, the height of the semiconductor package is lower than the design of disposing the semiconductor die on top of the interposer.

公开(公告)号：US09305902B1

公开(公告)日：2016-04-05

申请号：US14964464

申请日：2015-12-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L21/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1435 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further includes a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions.

公开(公告)号：US09240381B2

公开(公告)日：2016-01-19

申请号：US14034975

申请日：2013-09-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1435 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further includes a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions.

Abstract translation: 半导体器件包括用于连接另一半导体器件的多个导体。 每个导体通过形成在衬底上形成的绝缘层或连接到通过衬底和绝缘层形成的直立垂直连接的上垂直连接而连接到半导体器件内的芯片选择焊盘。 半导体器件还包括通过衬底形成的多个下垂直连接，并且相应地连接到芯片选择焊盘和芯片选择端。 芯片选择端子电连接到半导体器件的管芯电路，而芯片选择焊盘与裸片电路电隔离。 下垂直连接和垂直垂直连接可以在两个方面布置。

公开(公告)号：US10229877B2

公开(公告)日：2019-03-12

申请号：US15189437

申请日：2016-06-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/544 ,  H01L25/11 ,  H01L25/00 ,  H01L25/065

Abstract: The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking alignment and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side.

公开(公告)号：US10170340B2

公开(公告)日：2019-01-01

申请号：US15851595

申请日：2017-12-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L23/28 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor structure includes a substrate; a chip disposed over the substrate; and a molding disposed over the substrate and surrounding the chip at a molding temperature. The warpage of the substrate is convex or about zero at the molding temperature or 10° C. more or less than the molding temperature.

公开(公告)号：US09812414B1

公开(公告)日：2017-11-07

申请号：US15186100

申请日：2016-06-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po Chun Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L24/02 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02165 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/05096 ,  H01L2224/05548 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/06 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A chip package includes a first substrate; a first insulation layer disposed over the first substrate; a conductive structure disposed within the first insulation layer; a buffering member embedded into the first insulation layer; a redistribution layer (RDL) electrically connected with the conductive structure and disposed over the conductive structure and the buffering member; and a second insulation layer disposed over the RDL, wherein a portion of the RDL is exposed from the second insulation layer and disposed over the buffering member.