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公开(公告)号：US12125776B2
公开(公告)日：2024-10-22
申请号：US17562936
申请日：2021-12-27
发明人： Weiping Li
IPC分类号： H01L23/538 , H01L21/48 , H01L23/00 , H01L23/498 , H01L25/00 , H01L25/065 , H01L23/14 , H01L23/15
CPC分类号： H01L23/49833 , H01L21/486 , H01L23/5381 , H01L24/11 , H01L24/14 , H01L25/0655 , H01L25/50 , H01L23/147 , H01L23/15 , H01L23/49816 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/80 , H01L2224/0603 , H01L2224/11462 , H01L2224/11912 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2224/16145 , H01L2224/16227 , H01L2224/80895 , H01L2224/80896
摘要： The present disclosure provides a method for forming a semiconductor package and the semiconductor package. The method comprises attaching an interconnect device to a semiconductor substrate, and flip-chip mounting at least two chips over the interconnect device and the semiconductor substrate. Each chip includes at least one first bump of a first height and at least one second bump of a second height formed on a front surface hereof, the second height being greater than the first height. The method further comprises bonding the at least one second conductive bump of each of the at least two chips to the upper surface of the semiconductor substrate and bonding the first conductive bump of each of the at least two chips to the upper surface of the interconnect device Thus, the method uses a relatively simple and low cost packaging process to achieve high-density interconnection wiring in a package.
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公开(公告)号：US11935851B2
公开(公告)日：2024-03-19
申请号：US17543194
申请日：2021-12-06
发明人： Hsih-Yang Chiu
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L24/03 , H01L24/04 , H01L24/13 , H01L24/11 , H01L2224/03462 , H01L2224/03845 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05008 , H01L2224/05012 , H01L2224/05016 , H01L2224/05078 , H01L2224/05082 , H01L2224/05563 , H01L2224/11912 , H01L2224/13027
摘要： The present disclosure provides a semiconductor structure including a substrate; a redistribution layer (RDL) disposed over the substrate, and including a dielectric layer over the substrate, a conductive plug extending within the dielectric layer, and a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump disposed over the conductive plug, wherein the bonding pad is at least partially in contact with the conductive plug and the conductive bump. Further, a method of manufacturing the semiconductor structure is also provided.
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公开(公告)号：US20240088080A1
公开(公告)日：2024-03-14
申请号：US18514466
申请日：2023-11-20
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/04 , H01L24/05 , H01L24/11 , H01L24/03 , H01L2224/0345 , H01L2224/0401 , H01L2224/05073 , H01L2224/05573 , H01L2224/05666 , H01L2224/05684 , H01L2224/11005 , H01L2224/11462 , H01L2224/11912 , H01L2224/13082 , H01L2224/13109 , H01L2224/13147
摘要： A cryogenic under bump metallization (UBM) stack includes an adhesion and barrier layer and a conductive pillar on the adhesion and barrier layer. The conductive pillar functions as a solder wetting layer of the UBM stack and has a thickness. An indium superconducting solder bump is on the conductive pillar. The thickness of the conductive pillar is sufficient to prevent intermetallic regions, which form in the conductive pillar at room temperature due to interdiffusion, from extending through the entire thickness of the conductive pillar to maintain the structural integrity of the UBM stack. The indium (In) solder bump may be formed through electroplating, with the conductive pillar being copper (Cu) and the adhesion and barrier layer being titanium tungsten (TiW) and a thin seed layer of copper (Cu), or a layer of titanium (Ti). The UBM stack eliminates the need for magnetic materials such as nickel (Ni) in the stack, making the stack suitable for cryogenic applications.
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公开(公告)号：US11894329B2
公开(公告)日：2024-02-06
申请号：US17809224
申请日：2022-06-27
发明人： Chao Wen Wang
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/11011 , H01L2224/1146 , H01L2224/1147 , H01L2224/11912
摘要： Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
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公开(公告)号：USRE46618E1
公开(公告)日：2017-11-28
申请号：US13870579
申请日：2013-08-20
IPC分类号： H01L21/00 , H01L21/82 , H01L21/44 , H01L23/532 , H01L23/00 , H01L23/528 , H01L23/31
CPC分类号： H01L23/53238 , H01L23/3121 , H01L23/3192 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L24/94 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/0235 , H01L2224/02375 , H01L2224/0239 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05024 , H01L2224/05073 , H01L2224/05166 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/11912 , H01L2224/13013 , H01L2224/13082 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/14133 , H01L2224/16225 , H01L2224/16245 , H01L2224/81191 , H01L2224/81424 , H01L2224/81447 , H01L2224/8146 , H01L2224/81815 , H01L2224/94 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/30107 , H01L2924/3841 , H01L2924/00014 , H01L2224/11 , H01L2224/03 , H01L2924/01028 , H01L2224/05193 , H01L2924/013 , H01L2924/00
摘要： A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.
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公开(公告)号：US09754907B2
公开(公告)日：2017-09-05
申请号：US15133514
申请日：2016-04-20
发明人： Roger Dugas , John Trezza
IPC分类号： B44C1/165 , B29C65/00 , H01L23/427 , H01L21/48 , H01L21/683 , H01L23/498 , H01L23/556 , H01L25/065 , H01L25/18 , H01S5/042 , H01S5/183 , H01L23/00 , H01L21/768 , H01L23/48 , H01L23/538 , H01L23/552 , H01L23/66 , H01L25/00 , H01L23/488 , H01S5/022
CPC分类号： H01L24/11 , H01L21/4853 , H01L21/6835 , H01L21/76898 , H01L23/427 , H01L23/48 , H01L23/481 , H01L23/488 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/02 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/75 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/68345 , H01L2221/68363 , H01L2221/68368 , H01L2223/6616 , H01L2223/6622 , H01L2224/02372 , H01L2224/0401 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/11912 , H01L2224/13012 , H01L2224/13021 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/1358 , H01L2224/136 , H01L2224/13609 , H01L2224/16146 , H01L2224/16237 , H01L2224/24226 , H01L2224/45111 , H01L2224/75 , H01L2224/75305 , H01L2224/81001 , H01L2224/81011 , H01L2224/81054 , H01L2224/81136 , H01L2224/81193 , H01L2224/81203 , H01L2224/81204 , H01L2224/81825 , H01L2224/81894 , H01L2224/83102 , H01L2224/92125 , H01L2225/06513 , H01L2225/06524 , H01L2225/06531 , H01L2225/06534 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06593 , H01L2225/06596 , H01L2924/00013 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01S5/02272 , H01S5/02276 , H01S5/0422 , H01S5/0425 , H01S5/183 , H01S5/18308 , H01S2301/176 , H01L2924/00014 , H01L2924/00
摘要： A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.
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公开(公告)号：US09721916B2
公开(公告)日：2017-08-01
申请号：US15255963
申请日：2016-09-02
发明人： Jung Wei Cheng , Tsung-Ding Wang , Chien-Hsun Lee
IPC分类号： H01L23/00 , H01L23/544 , H01L21/78 , H01L25/065 , H01L25/00
CPC分类号： H01L24/14 , H01L21/78 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2223/5442 , H01L2223/54426 , H01L2223/54486 , H01L2224/0214 , H01L2224/0215 , H01L2224/0345 , H01L2224/0361 , H01L2224/03622 , H01L2224/03912 , H01L2224/0401 , H01L2224/05008 , H01L2224/05011 , H01L2224/05012 , H01L2224/05013 , H01L2224/05014 , H01L2224/05015 , H01L2224/05024 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05551 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05558 , H01L2224/05562 , H01L2224/05569 , H01L2224/05572 , H01L2224/0558 , H01L2224/05582 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05681 , H01L2224/05684 , H01L2224/0603 , H01L2224/06051 , H01L2224/06132 , H01L2224/06179 , H01L2224/06517 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13023 , H01L2224/13026 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13562 , H01L2224/13639 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2224/1403 , H01L2224/14051 , H01L2224/14104 , H01L2224/14132 , H01L2224/14134 , H01L2224/14179 , H01L2224/14517 , H01L2224/16013 , H01L2224/16058 , H01L2224/16059 , H01L2224/16148 , H01L2224/16238 , H01L2224/17051 , H01L2224/17515 , H01L2224/17517 , H01L2224/81007 , H01L2224/81139 , H01L2224/81141 , H01L2224/81193 , H01L2224/81194 , H01L2224/81345 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06565 , H01L2225/06593 , H01L2924/01022 , H01L2924/01073 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00014 , H01L2924/013 , H01L2224/03 , H01L2224/11 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029
摘要： An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.
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8.发明申请公开(公告)号：US20170141062A1
公开(公告)日：2017-05-18
申请号：US15419064
申请日：2017-01-30
申请人： Intel Corporation
发明人： Madhav Datta , Dave Emory , Subhash M. Joshi , Susanne Menezes , Doowon Suh
IPC分类号： H01L23/00
CPC分类号： H01L24/11 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05572 , H01L2224/05647 , H01L2224/10126 , H01L2224/11009 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/11901 , H01L2224/11912 , H01L2224/13023 , H01L2224/13099 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/13166 , H01L2924/0002 , H01L2924/01005 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0104 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01057 , H01L2924/01058 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/05552
摘要： The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.
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公开(公告)号：US09613926B2
公开(公告)日：2017-04-04
申请号：US14712729
申请日：2015-05-14
发明人： Chen-Hua Yu , Ming-Fa Chen , Wen-Ching Tsai
CPC分类号： H01L24/81 , B81C1/00238 , B81C3/001 , B81C2203/031 , B81C2203/035 , H01L21/50 , H01L23/10 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/83 , H01L24/92 , H01L24/94 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/03602 , H01L2224/03614 , H01L2224/03616 , H01L2224/03912 , H01L2224/0401 , H01L2224/04026 , H01L2224/05022 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05149 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05548 , H01L2224/05567 , H01L2224/05569 , H01L2224/05571 , H01L2224/056 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05684 , H01L2224/06051 , H01L2224/08225 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11614 , H01L2224/119 , H01L2224/11912 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13149 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/16014 , H01L2224/16147 , H01L2224/2745 , H01L2224/27452 , H01L2224/27462 , H01L2224/27464 , H01L2224/2747 , H01L2224/27614 , H01L2224/279 , H01L2224/27912 , H01L2224/29011 , H01L2224/29013 , H01L2224/29014 , H01L2224/29082 , H01L2224/291 , H01L2224/29111 , H01L2224/29124 , H01L2224/29138 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29149 , H01L2224/29155 , H01L2224/29164 , H01L2224/29166 , H01L2224/32014 , H01L2224/32147 , H01L2224/32225 , H01L2224/73103 , H01L2224/80805 , H01L2224/80893 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2224/81815 , H01L2224/8183 , H01L2224/83805 , H01L2224/83815 , H01L2224/8383 , H01L2224/92 , H01L2224/9202 , H01L2224/94 , H01L2924/10158 , H01L2924/1461 , H01L2924/163 , H01L2924/00014 , H01L2924/01014 , H01L2224/03 , H01L2224/11 , H01L2224/27 , H01L2924/00012 , H01L2224/0347 , H01L2924/014 , H01L2224/81 , H01L2224/83 , H01L2224/114 , H01L2224/1146 , H01L2224/1161 , H01L2224/274 , H01L2224/2746 , H01L2224/2761 , H01L21/302 , H01L2224/034 , H01L2224/0361 , H01L2224/80
摘要： Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.
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公开(公告)号：US09324629B2
公开(公告)日：2016-04-26
申请号：US11693984
申请日：2007-03-30
申请人： Roger Dugas , John Trezza
发明人： Roger Dugas , John Trezza
IPC分类号： B44C1/165 , B29C65/00 , H01L23/427 , H01L21/48 , H01L21/683 , H01L21/768 , H01L23/48 , H01L23/498 , H01L23/538 , H01L23/552 , H01L23/66 , H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00 , H01S5/042 , H01L23/488 , H01S5/022 , H01S5/183
CPC分类号： H01L24/11 , H01L21/4853 , H01L21/6835 , H01L21/76898 , H01L23/427 , H01L23/48 , H01L23/481 , H01L23/488 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/02 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/75 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/68345 , H01L2221/68363 , H01L2221/68368 , H01L2223/6616 , H01L2223/6622 , H01L2224/02372 , H01L2224/0401 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/11912 , H01L2224/13012 , H01L2224/13021 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/1358 , H01L2224/136 , H01L2224/13609 , H01L2224/16146 , H01L2224/16237 , H01L2224/24226 , H01L2224/45111 , H01L2224/75 , H01L2224/75305 , H01L2224/81001 , H01L2224/81011 , H01L2224/81054 , H01L2224/81136 , H01L2224/81193 , H01L2224/81203 , H01L2224/81204 , H01L2224/81825 , H01L2224/81894 , H01L2224/83102 , H01L2224/92125 , H01L2225/06513 , H01L2225/06524 , H01L2225/06531 , H01L2225/06534 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06593 , H01L2225/06596 , H01L2924/00013 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01S5/02272 , H01S5/02276 , H01S5/0422 , H01S5/0425 , H01S5/183 , H01S5/18308 , H01S2301/176 , H01L2924/00014 , H01L2924/00
摘要： A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.
摘要翻译： 一种使用多个芯片的方法，每个芯片分别具有包括电触点的接合表面和与接合表面相对的一侧的表面，包括使位于主体上的可硬化材料与多个芯片接触，硬化可硬化材料，从而 约束多个芯片中的每一个的至少一部分，将多个芯片从第一位置移动到第二位置，向身体施加力，使得硬化的可硬化材料将均匀地传递施加到身体的垂直力， 以在每个单独的芯片的接合表面与第二位置处的单个芯片将被接合的元件的接合表面接触的同时，不会对各个芯片元件造成损害， ，或粘结面。
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