公开(公告)号：US20230299067A1

公开(公告)日：2023-09-21

申请号：US18324743

申请日：2023-05-26

申请人： International Business Machines Corporation

发明人： Akihiro Horibe ,  Takahito Watanabe ,  Toyohiro Aoki ,  Takashi Hisada ,  Hiroyuki Mori

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L25/50 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L23/538 ,  H01L2224/83951 ,  H01L2224/75981 ,  H01L2224/75755 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/92125 ,  H01L2224/75101

摘要： Interconnecting a first chip and a second chip includes mounting the first and second chips to a chip handler having an opening and at least one support surface. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The first surface of the first chip and the first surface of the second chip mounted to the chip handler are supported by the at least one support surface of the chip handler. The first and second chips are placed on a chip support member with the chip handler from the second surfaces. A bridge member is inserted by a bridge handler through the opening of the chip handler to place the bridge member onto the first sets of terminals of the first and second chips that are exposed from the opening.

公开(公告)号：US11735575B2

公开(公告)日：2023-08-22

申请号：US17303333

申请日：2021-05-27

申请人： International Business Machines Corporation

发明人： Akihiro Horibe ,  Takahito Watanabe ,  Toyohiro Aoki ,  Takashi Hisada ,  Hiroyuki Mori

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L25/50 ,  H01L23/538 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/75101 ,  H01L2224/75755 ,  H01L2224/75981 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/83951 ,  H01L2224/92125

摘要： Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.

公开(公告)号：US20180033754A1

公开(公告)日：2018-02-01

申请号：US15664158

申请日：2017-07-31

申请人： Cufer Asset Ltd. L.L.C.

发明人： Roger Dugas ,  John Trezza

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L25/18 ,  H01L25/065 ,  H01L23/66 ,  H01L23/552 ,  H01L23/538 ,  H01L23/498 ,  H01L23/488 ,  H01L23/48 ,  H01L23/427 ,  H01L21/768 ,  H01L21/683 ,  H01L25/00 ,  H01S5/042 ,  H01S5/183 ,  H01S5/022

CPC分类号： H01L24/11 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/24226 ,  H01L2224/45111 ,  H01L2224/75 ,  H01L2224/75305 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81825 ,  H01L2224/81894 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/183 ,  H01S5/18308 ,  H01S2301/176 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.

公开(公告)号：US09686895B2

公开(公告)日：2017-06-20

申请号：US14017311

申请日：2013-09-04

申请人： International Business Machines Corporation

发明人： Martin Eckert ,  Otto Torreiter ,  Quintino L. Trianni

IPC分类号： H05K13/04 ,  H01L23/00 ,  G01R1/04

CPC分类号： H01L24/75 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/4853 ,  H01L21/67144 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75315 ,  H01L2224/75316 ,  H01L2224/75501 ,  H01L2224/757 ,  H01L2224/75754 ,  H01L2224/75756 ,  H01L2224/759 ,  H01L2224/81121 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81908 ,  H05K13/0413 ,  Y10T29/53178 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

摘要： A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.

公开(公告)号：US09508665B2

公开(公告)日：2016-11-29

申请号：US12831919

申请日：2010-07-07

申请人： Eric Beyne ,  Paresh Limaye

发明人： Eric Beyne ,  Paresh Limaye

IPC分类号： H01L21/30 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method for insertion bonding and a device thus obtained are disclosed. In one aspect, the device includes a first substrate having a front main surface and at least one protrusion at the front main surface. The device includes a second substrate having a front main surface and at least one hole extending from the front main surface into the second substrate. The protrusion of the first substrate is inserted into the hole of the second substrate. The hole is formed in a shape wherein the width is reduced in the depth direction and wherein the width of at least a part of the hole is smaller than the width of the protrusion at the location of the metal portion thereof. The protrusion is deformed during insertion thereof in the hole to provide a bond between the part of the hole and the metal portion.

摘要翻译： 公开了一种用于插入接合的方法和由此获得的器件。 一方面，该装置包括具有前主表面和在前主表面处的至少一个突起的第一基底。 该装置包括具有前主表面和从前主表面延伸到第二基板的至少一个孔的第二基板。 将第一基板的突起插入第二基板的孔中。 孔形成为宽度在深度方向上减小的形状，并且其中孔的至少一部分的宽度小于在其金属部分的位置处的突起的宽度。 突起在其插入孔期间变形，以在孔的一部分和金属部分之间形成结合。

公开(公告)号：US20160133554A1

公开(公告)日：2016-05-12

申请号：US14997846

申请日：2016-01-18

申请人： International Business Machines Corporation

发明人： Jae-Woong Nah ,  Charles L. Reynolds ,  Katsuyuki Sakuma

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49816 ,  H01L21/0334 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/08238 ,  H01L2224/10165 ,  H01L2224/11005 ,  H01L2224/11466 ,  H01L2224/11849 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81136 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/07802 ,  H01L2924/15311 ,  H05K1/00 ,  H05K3/3436 ,  H05K3/3478 ,  H05K3/4007 ,  H05K7/10 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/047 ,  H05K2203/048 ,  H05K2203/167 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

摘要： Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.

摘要翻译： 在图案化的临时抗蚀剂中的层压板的背面上形成球栅组件（BGA）凸块焊料。 诸如单片化和倒装芯片组件的处理是在临时抗蚀剂就位后进行的。 在卡组装之前，将抗蚀剂从单层叠板的背面去除。 具有相对较高熔点的分离元件可以被结合到层压板的BGA侧，以确保最小组装焊料塌陷高度。 使用具有相对较高熔点和注入的焊料的元件，在LGA模块的面向插座的侧面上形成对准组件。

公开(公告)号：US20160035659A1

公开(公告)日：2016-02-04

申请号：US14451411

申请日：2014-08-04

申请人： International Business Machines Corporation

发明人： Jae-Woong Nah ,  Charles L. Reynolds ,  Katsuyuki Sakuma

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/033

CPC分类号： H01L23/49816 ,  H01L21/0334 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/08238 ,  H01L2224/10165 ,  H01L2224/11005 ,  H01L2224/11466 ,  H01L2224/11849 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81136 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/07802 ,  H01L2924/15311 ,  H05K1/00 ,  H05K3/3436 ,  H05K3/3478 ,  H05K3/4007 ,  H05K7/10 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/047 ,  H05K2203/048 ,  H05K2203/167 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

摘要： Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.

公开(公告)号：US09159665B2

公开(公告)日：2015-10-13

申请号：US13645397

申请日：2012-10-04

申请人： STATS ChipPAC, Ltd.

发明人： Rajendra D. Pendse

IPC分类号： H01L21/60 ,  H01L23/488 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H05K1/11 ,  H05K3/34

CPC分类号： H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

摘要翻译： 通过将互连凸块配合到引线或迹线上的窄互连焊盘而不是捕获板上，来制造衬底上的管芯的倒装芯片互连。 窄互连焊盘的宽度小于要连接的裸片上的凸块的基底直径。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中的导电迹线上具有窄互连焊盘的衬底，其中凸块配合到 痕迹

公开(公告)号：US09147635B2

公开(公告)日：2015-09-29

申请号：US12966699

申请日：2010-12-13

申请人： John Trezza ,  John Callahan ,  Gregory Dudoff

发明人： John Trezza ,  John Callahan ,  Gregory Dudoff

IPC分类号： H01L21/48 ,  H01L23/427 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/488 ,  H01S5/022 ,  H01S5/042 ,  H01S5/183

CPC分类号： H01L24/11 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/24226 ,  H01L2224/45111 ,  H01L2224/75 ,  H01L2224/75305 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81825 ,  H01L2224/81894 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/183 ,  H01S5/18308 ,  H01S2301/176 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip.

摘要翻译： 两个芯片之间的电连接包括第一芯片上的IC焊盘，第二芯片上的IC焊盘，第一芯片的IC焊盘上的第一势垒金属，第二芯片的IC焊盘上的第二阻挡金属， 与第一阻挡金属和第二阻挡金属之间的阻挡金属不同的可延展的导电金属，第一阻挡金属，有韧性的导电金属和第二阻挡金属在第一和第二阻挡金属的IC垫之间形成完整的导电路径 芯片和第二芯片的IC焊盘。

公开(公告)号：US20150255374A1

公开(公告)日：2015-09-10

申请号：US14716791

申请日：2015-05-19

申请人： Tessera Advanced Technologies, Inc.

发明人： Michihiro Kawashita ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

IPC分类号： H01L23/48 ,  H01L23/528 ,  H01L25/07 ,  H01L23/522

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/274 ,  H01L2224/81136 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81801 ,  H01L2224/81898 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1451 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.

摘要翻译： 在层叠多个半导体芯片的半导体装置中，不会降低生产率而提高性能。 半导体器件具有第一半导体衬底，其具有与第一表面相对的第一表面和第二表面，形成在第一表面上的第一绝缘膜，形成在第一绝缘膜中并部分延伸到第一半导体衬底中的第一孔， 在第二表面上形成的第二孔，完全填充第一孔的第一电极和在第二孔中共形形成的导电膜。 导电膜电连接到第一电极的底表面，并使第一半导体衬底中的第三孔断开。 第三孔构造成接收第二半导体衬底的第二电极。