公开(公告)号：US09957411B2

公开(公告)日：2018-05-01

申请号：US14915734

申请日：2014-09-10

Applicant: DEXERIALS CORPORATION

Inventor： Takayuki Saito ,  Taichi Koyama ,  Hironobu Moriyama

IPC: C09J7/00 ,  C09J163/00 ,  C09J133/08 ,  C09J133/10 ,  C09D163/00 ,  C09J133/04 ,  C09J163/08 ,  H01L21/683 ,  H01L23/29 ,  H01L21/56 ,  C09D133/06 ,  C09J133/06 ,  H01L23/31 ,  C08G59/42 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: C09D163/00 ,  C08G59/42 ,  C08L63/00 ,  C09D133/066 ,  C09J133/04 ,  C09J133/066 ,  C09J163/08 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/293 ,  H01L23/3142 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83204 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/0635 ,  H01L2924/05442 ,  H01L2924/05341 ,  H01L2924/0549 ,  H01L2924/0532 ,  H01L2924/0102 ,  H01L2924/0544 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L21/78 ,  C08K5/14 ,  C08L33/10

Abstract: An underfill material achieving a wide margin for mounting and a method for manufacturing a semiconductor device using the same are provided. The underfill material contains an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide, wherein a minimum melt viscosity attainment temperature and a minimum melt viscosity obtained when melt viscosity of the underfill material is measured under a temperature increase rate condition in a range of 5 to 50° C./min are in a range of 100° C. to 150° C. and in a range of 100 to 5000 Pa·s, respectively. Since variation in the minimum melt viscosity attainment temperature measured under different temperature increase conditions is small, voidless mounting and good solder bonding properties can be achieved without strict control on the temperature profile during thermocompression bonding, and a wide margin for mounting can be achieved.

公开(公告)号：US09659902B2

公开(公告)日：2017-05-23

申请号：US14627210

申请日：2015-02-20

Applicant: Kulicke and Soffa Industries, Inc.

Inventor： Matthew B. Wasserman

IPC: H01L21/00 ,  H03K3/00 ,  H01L23/00 ,  H01L21/67 ,  H05K3/34

CPC classification number: H01L24/81 ,  B32B37/0046 ,  B32B37/06 ,  B32B2457/14 ,  H01L21/67092 ,  H01L21/67109 ,  H01L21/67144 ,  H01L21/67248 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/75252 ,  H01L2224/7531 ,  H01L2224/75502 ,  H01L2224/759 ,  H01L2224/75981 ,  H01L2224/81048 ,  H01L2224/81092 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/81948 ,  H05K3/3494 ,  H05K2203/0475 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A thermocompression bonding system for bonding semiconductor elements is provided. The thermocompression bonding system includes (1) a bond head assembly including a heater for heating an semiconductor element to be bonded, the bond head assembly including a fluid path configured to receive a cooling fluid; (2) a pressurized cooling fluid source; (3) a booster pump for receiving a pressurized cooling fluid from the pressurized cooling fluid source, and for increasing a pressure of the received pressurized cooling fluid; (4) a pressurized fluid reservoir for receiving pressurized cooling fluid from the booster pump; and (5) a control valve for controlling a supply of pressurized cooling fluid from the pressurized fluid reservoir to the fluid path.

公开(公告)号：US09478458B2

公开(公告)日：2016-10-25

申请号：US14149965

申请日：2014-01-08

Applicant: Northrop Grumman Systems Corporation

Inventor： Chunbo Zhang ,  Peter Ngo ,  Gershon Akerling ,  Kevin M. Leong ,  Patty Chang-Chien ,  Kelly J. Hennig ,  William R. Deal

IPC: H01Q13/02 ,  H01L21/762 ,  H01L23/66 ,  H01Q23/00 ,  H01L23/055 ,  H01L23/14 ,  H01P11/00 ,  H01L23/00

CPC classification number: H01L27/14685 ,  H01L21/76254 ,  H01L23/055 ,  H01L23/147 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L27/14687 ,  H01L31/186 ,  H01L31/1876 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/81054 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81204 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/14215 ,  H01L2924/1423 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/37001 ,  H01P11/002 ,  H01Q13/02 ,  H01Q23/00 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/01079

Abstract: A method and apparatus for integrating individual III-V MMICs into a micromachined waveguide package is disclosed. MMICs are screened prior to integration, allowing only known-good die to be integrated, leading to increased yield. The method and apparatus are used to implement a micro-integrated Focal Plane Array (mFPA) technology used for sub millimeter wave (SMMW) cameras, although many other applications are possible. MMICs of different technologies may be integrated into the same micromachined package thus achieving the same level of technology integration as in multi-wafer WLP integration.

Abstract translation: 公开了一种用于将单个III-V MMIC集成到微加工波导封装中的方法和装置。 MMIC在集成之前进行筛选，仅允许已知的芯片集成，从而提高产量。 该方法和装置用于实现用于亚毫米波（SMMW）相机的微集成焦平面阵列（mFPA）技术，尽管许多其他应用是可能的。 不同技术的MMIC可以集成到相同的微加工包装中，从而实现与多晶圆WLP集成相同的技术集成水平。

公开(公告)号：US09391031B2

公开(公告)日：2016-07-12

申请号：US13922332

申请日：2013-06-20

Applicant: FUJITSU LIMITED

Inventor： Tetsuya Takahashi ,  Yasuo Moriya ,  Kimio Nakamura

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/07 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75314 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81208 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/83209 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/92242 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A method for manufacturing an electronic device, the method includes: applying an adhesive film on a package board; placing an electronic component on the package board with a bump therebetween; applying a first load to the electronic component while heating the electronic component to a first temperature higher than a reaction start temperature of the adhesive film and lower than a melting point of the bump; reducing the first load to a second load lower than the first load while maintaining the first temperature; and heating the electronic component to a second temperature higher than or equal to the melting point of the bump while maintaining the second load.

Abstract translation: 一种电子设备的制造方法，其特征在于，包括：在封装板上涂布粘合膜; 将电子部件放置在封装板上，其间具有凸块; 在将电子部件加热至高于粘合膜的反应开始温度的第一温度并低于凸点的熔点的同时向电子部件施加第一负载; 在保持第一温度的同时将第一负载减小到低于第一负载的第二负载; 并且在保持第二负载的同时将电子部件加热到高于或等于凸点的熔点的第二温度。

公开(公告)号：US20160194517A1

公开(公告)日：2016-07-07

申请号：US14915734

申请日：2014-09-10

Applicant: DEXERIALS CORPORATION

Inventor： Takayuki SAITO ,  Taichi KOYAMA ,  Hironobu MORIYAMA

IPC: C09D163/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: C09D163/00 ,  C08G59/42 ,  C08L63/00 ,  C09D133/066 ,  C09J133/04 ,  C09J133/066 ,  C09J163/08 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/293 ,  H01L23/3142 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83204 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/0635 ,  H01L2924/05442 ,  H01L2924/05341 ,  H01L2924/0549 ,  H01L2924/0532 ,  H01L2924/0102 ,  H01L2924/0544 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L21/78 ,  C08K5/14 ,  C08L33/10

Abstract: An underfill material achieving a wide margin for mounting and a method for manufacturing a semiconductor device using the same are provided. The underfill material contains an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide, wherein a minimum melt viscosity attainment temperature and a minimum melt viscosity obtained when melt viscosity of the underfill material is measured under a temperature increase rate condition in a range of 5 to 50° C./min are in a range of 100° C. to 150° C. and in a range of 100 to 5000 Pa·s, respectively. Since variation in the minimum melt viscosity attainment temperature measured under different temperature increase conditions is small, voidless mounting and good solder bonding properties can be achieved without strict control on the temperature profile during thermocompression bonding, and a wide margin for mounting can be achieved.

Abstract translation: 提供了用于安装的宽裕度的底部填充材料和使用其的制造半导体器件的方法。 底部填充材料含有环氧树脂，酸酐，丙烯酸树脂和有机过氧化物，其中在底物填充材料的熔融粘度在温度升高速率条件下测定时获得的最小熔体粘度达到温度和最小熔体粘度 5〜50℃/分钟的范围分别为100〜150℃，范围为100〜5000Pa·s。 由于在不同温度升高条件下测量的最小熔融粘度达到温度的变化小，无需严格控制热压接温度分布，就可以实现无孔安装和良好的焊接性能，并且可以实现大的安装余地。

公开(公告)号：US20160084638A1

公开(公告)日：2016-03-24

申请号：US14923676

申请日：2015-10-27

Applicant: BONDTECH CO., LTD.

Inventor： Akira YAMAUCHI

IPC: G01B11/14

CPC classification number: H01L24/75 ,  G01B11/14 ,  H01L23/544 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/757 ,  H01L2224/81009 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/83121 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0107 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K1/0269 ,  H05K3/303 ,  H05K2201/09918 ,  H05K2203/166 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A pressure application technique is provided that enables two objects to be pressurized (e.g., objects to be bonded) to be positioned with greater accuracy before having pressure applied thereto. The objects to be pressurized are moved relative to each other in a Z direction such that the objects are brought into contact with each other (step S13). Then, a horizontal positional shift ΔD between the objects to be pressurized is measured in the contact state of the objects to be pressurized (step S14). Thereafter, positioning of the objects to be pressurized is again performed by moving the objects to be pressurized relative to each other in the horizontal direction, as a result of which the positional shift ΔD is corrected (step S17).

Abstract translation: 提供了一种压力施加技术，其能够在施加压力之前使两个物体被加压（例如，待粘合的物体）以更高的准确度定位。 要加压的物体在Z方向上彼此相对移动，使得物体彼此接触（步骤S13）。 然后，在待加压物体的接触状态下测量待加压物体之间的水平位置移动量Dgr; D（步骤S14）。 此后，通过在水平方向上相对于彼此移动要加压的物体来再次执行要加压的物体的定位，结果校正位置偏移＆Dgr; D（步骤S17）。

公开(公告)号：US20160064297A1

公开(公告)日：2016-03-03

申请号：US14779839

申请日：2014-03-19

Applicant: NITTO DENKO CORPORATION

Inventor： Kosuke Morita ,  Naohide Takamoto

IPC: H01L23/29 ,  B32B7/12 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/29 ,  B32B7/12 ,  B32B2307/51 ,  B32B2457/14 ,  C09K3/1006 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/293 ,  H01L23/544 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/2744 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29318 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29371 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75753 ,  H01L2224/81123 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/83123 ,  H01L2224/83191 ,  H01L2224/83204 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/01006 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83 ,  H01L21/304 ,  H01L21/78 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Provided are an under-fill material which is capable of reducing a difference in thermal response behavior between a semiconductor element and an adherend and which makes it easy and convenient to perform alignment for mounting the semiconductor element, a sealing sheet including the under-fill material, and a method for producing a semiconductor device using the under-fill material. In the under-fill material of the present invention, a haze is 70% or less before a heat curing treatment, and a storage elastic modulus E′ [MPa] and a thermal expansion coefficient α [ppm/K] after the under-fill material is subjected to a heat curing treatment at 175° C. for 1 hour satisfy the following formula (1) at 25° C.: 10000

Abstract translation: 提供了能够减少半导体元件和被粘物之间的热响应行为差异的填充不足的材料，并且使得对于安装半导体元件进行对准变得容易和方便，包括填充材料的密封片 以及使用该填充不足的材料制造半导体器件的方法。 在本发明的填充不足的材料中，在热固化处理之前的雾度为70％以下，填充后的储能弹性模量E'[MPa]和热膨胀系数α[ppm / K] 材料在25℃下在175℃下进行热固化处理1小时，满足下式（1）：10000

公开(公告)号：US20150212340A1

公开(公告)日：2015-07-30

申请号：US14678198

申请日：2015-04-03

Applicant: Google Inc.

Inventor： James Etzkorn

IPC: G02C11/00 ,  H01L23/31 ,  H01L21/768 ,  H01L23/528 ,  H01L21/56 ,  H01L23/00

CPC classification number: G02C11/10 ,  A61B5/6821 ,  A61B2562/12 ,  B29D11/00048 ,  B29D11/00807 ,  G02C7/04 ,  G02C7/049 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/97 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/08225 ,  H01L2224/11312 ,  H01L2224/13109 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8012 ,  H01L2224/8085 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00 ,  H01L2224/83104 ,  H01L2224/05599 ,  H01L2924/013 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/00013 ,  H01L2924/20105 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A contact lens having a thin silicon chip integrated therein is provided along with methods for assembling the silicon chip within the contact lens. In an aspect, a method includes creating a plurality of lens contact pads on a lens substrate and creating a plurality of chip contact pads on a chip. The method further involves applying assembly bonding material to the each of the plurality of lens contact pads or chip contact pads, aligning the plurality of lens contact pads with the plurality of chip contact pads, bonding the chip to the lens substrate via the assembly bonding material using flip chip bonding, and forming a contact lens with the lens substrate.

Abstract translation: 集成有薄硅芯片的隐形眼镜与隐形眼镜中的硅芯片的组装方法一起提供。 一方面，一种方法包括在透镜基板上形成多个透镜接触焊盘并在芯片上产生多个芯片接触焊盘。 该方法还包括将组装接合材料施加到多个透镜接触焊盘或芯片接触焊盘中的每一个上，将多个透镜接触焊盘与多个芯片接触焊盘对准，通过组装接合材料将芯片粘合到透镜基板 使用倒装芯片接合，并且与透镜基板形成隐形眼镜。

公开(公告)号：US08936968B2

公开(公告)日：2015-01-20

申请号：US13534073

申请日：2012-06-27

Applicant: Horng Chih Horng

Inventor： Horng Chih Horng

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/78 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L21/78 ,  H01L21/563 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/81908 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83908 ,  H01L2224/83948 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/3641 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A flip chip package manufacturing method is provided. A non-conductive film is pressed onto a wafer with multiple conductive bumps. The wafer is cut to multiple single chips. A carrier is provided, and a thermo-compression flip chip bonding process is executed to bond the non-conductive film onto the carrier. The carrier is transferred into a chamber with enclosed, pneumatic pressurized and heatingable characteristics to execute a de-void process to eliminate the bubbles and to execute a high-temperature soldering process to solder the single chip onto the carrier. The sequence of the de-void process and the high-temperature soldering process may exchange.

Abstract translation: 提供了一种倒装芯片封装制造方法。 将非导电膜压在具有多个导电凸块的晶片上。 将晶片切割成多个单个芯片。 提供载体，并且执行热压缩倒装芯片接合工艺以将非导电膜结合到载体上。 载体被转移到具有封闭的气动加压和可加热特性的室中，以执行去空气处理以消除气泡并执行高温焊接工艺以将单个芯片焊接到载体上。 脱泡过程和高温焊接过程的顺序可以交换。

公开(公告)号：US08846445B2

公开(公告)日：2014-09-30

申请号：US13164193

申请日：2011-06-20

Applicant: John Trezza

Inventor： John Trezza

IPC: H01L21/00 ,  H01S5/042 ,  H01L23/498 ,  H01L23/00 ,  H01L23/427 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768 ,  H01L25/065 ,  H01L23/66 ,  H01L21/683 ,  H01L23/538 ,  H01L23/552 ,  H01S5/183 ,  H01S5/022

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/24226 ,  H01L2224/45111 ,  H01L2224/75 ,  H01L2224/75305 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81825 ,  H01L2224/81894 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/183 ,  H01S5/18308 ,  H01S2301/176 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A system for connecting a first chip to a second chip having a post on the first chip having a first metallic material, a recessed wall within the second chip and defining a well within the second chip, a conductive diffusion layer material on a surface of the recessed wall within the well, and a malleable electrically conductive material on the post, the post being dimensioned for insertion into the well such that the malleable electrically conductive material will deform within the well and, upon heating to at least a tack temperature for the malleable, electrically conductive material, will form an electrically conductive tack connection with the diffusion layer to create an electrically conductive path between the first chip and the second chip.

Abstract translation: 一种用于将第一芯片连接到具有第一芯片上的柱的第二芯片的系统，具有第一金属材料，第二芯片内的凹陷壁，并且在第二芯片内限定阱，在所述第二芯片的表面上的导电扩散层材料 凹陷的壁，以及位于柱上的可延展的导电材料，该柱的尺寸被设计成用于插入到井中，使得可延展的导电材料将在孔内变形，并且在加热至至少一个粘性温度用于可延展的 导电材料将形成与扩散层的导电粘性连接，以在第一芯片和第二芯片之间形成导电路径。