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    Wafer via formation
    6.
    发明授权
    Wafer via formation 失效
    晶圆通过形成

    公开(公告)号：US07871927B2

    公开(公告)日：2011-01-18

    申请号：US11872083

    申请日：2007-10-15

    Applicant: John Trezza

    Inventor： John Trezza

    IPC: H01L21/445

    CPC classification number: H01L21/76898

    Abstract: A method of electrically conductive via formation in a fully processed wafer involves defining at least one trench area on a backside of the fully processed wafer, forming at least one trench within the trench area to an overall depth that will allow for a via formed within the trench to be seeded over its full length, forming the via within the trench into the fully processed wafer to a predetermined depth, depositing a seed layer over the full length of the via, and plating the seed layer to fill the via with an electrically conductive metal.

    Abstract translation: 在完全处理的晶片中的导电通孔形成的方法包括限定完全处理的晶片的背面上的至少一个沟槽区域，在沟槽区域内形成至少一个沟槽，以使得能够在 要在其全长上接种的沟槽，在沟槽内形成通孔进入完全处理的晶片到预定深度，在通孔的整个长度上沉积种子层，并且电镀种子层以用电 导电金属。

    Sensitivity capacitive sensor
    9.
    发明授权
    Sensitivity capacitive sensor 有权
    灵敏度电容传感器

    公开(公告)号：US07705613B2

    公开(公告)日：2010-04-27

    申请号：US11619482

    申请日：2007-01-03

    Applicant: Abhay Misra ,  John Trezza

    Inventor： Abhay Misra ,  John Trezza

    IPC: G01R27/26 ,  G06K9/00

    CPC classification number: G06K9/0002 ,  H01L2224/48091 ,  H01L2224/8592 ,  Y10T29/49002 ,  Y10T29/49007 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00014

    Abstract: A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electrically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25 μm. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less than 25 μm.

    Abstract translation: 创建改进的灵敏度电容指纹传感器的方法包括从具有电容传感器阵列的传感器芯片的第一侧形成通孔，使得通孔导电，并且将覆盖板附接在传感器芯片的与第一侧隔开的第一侧上 传感器芯片距离小于25μm。 改进的灵敏度电容式指纹传感器具有电容式传感器阵列，其包括多个传感器单元和从用于传感器单元电路的连接点延伸到电容式传感器阵列背面的导电的通孔，包括主动检测电路和电连接 点，电连接点分别连接到相应的传感器单元电路连接点，以及盖板，设置在传感器单元上​​方，间隔小于25μm。

    Plated pillar package formation
    10.
    发明授权
    Plated pillar package formation 失效
    电镀柱包装形成

    公开(公告)号：US07670874B2

    公开(公告)日：2010-03-02

    申请号：US11675731

    申请日：2007-02-16

    Applicant: John Trezza

    Inventor： John Trezza

    IPC: H01L21/00

    CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method involves plating pillars of electrically conductive material up from a seed layer located on a substrate, surrounding the pillars with a fill material so that the pillars and fill material collectively define a first package, and removing the substrate from the first package.

    Abstract translation: 一种方法包括从位于基底上的晶种层上覆盖导电材料的柱，用填充材料围绕柱子，使得柱和填充材料共同限定第一封装，并从第一封装移除衬底。

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